MACH211SP-10VC データシートの表示（PDF） - Lattice Semiconductor

部品番号

コンポーネント説明

メーカー

MACH211SP-10VC

High-Performance EE CMOS Programmable Logic

Lattice Semiconductor 

Feature

Macrocells

Maximum user I/O pins

tP D (ns)

tS (ns)

tCO (ns)

fCNT (MHz)

Table 1. MACH 1 and 2 Family Device Features 1

MACH111 (SP)

32

32

5.0

3.5

3.5

182

MACH131 (SP)

64

64

5.5

3.0

4

182

MACH211 (SP)

64

32

7.5 (6.0)

5.5 (5)

4.5 (4)

133 (166)

MACH221 (SP)

96

48

7.5

5.5

5

133

Note:

1. Values in parentheses ( ) are for the SP version.

MACH231 (SP)

128

64

6.0 (10)

5 (6.5)

4 (6.5)

166 (100)

GENERAL DESCRIPTION

The MACH® 1 & 2 families from Lattice/Vantis offer high-performance, low cost Complex

Programmable Logic Devices (CPLDs), addressing the growing need for speed in networking,

telecommunications and computing. MACH 1 & 2 devices are available in speeds as fast as 5.0-ns

tPD and in densities ranging from 32 to 128 macrocells (Tables 1 and 2). The overall benefits for

users include guaranteed high performance for entry-to-mid-level logic needs at a low cost.

Table 2. MACH 1 and 2 Family Speed Grades1

MACH111

MACH111SP

MACH131

MACH131SP

MACH211

MACH211SP

MACH221

MACH221SP

MACH231

MACH231SP

Device

-5

-6

C (Note 2)

C (Note 2)

C (Note 3)

C (Note 3)

C

C

-7

-10

-12

-14

-15

-18

C, I

C, I

C, I

I

C

I

C, I

C, I

C, I

I

C

I

C, I

C, I

C, I

I

C

I

C, I

C, I

C, I

I

C

I

C

C, I

C, I

I

C

I

C

C, I

C, I

I

C

I

C

C, I

C, I

I

C

I

C

C, I

C, I

I

C

I

C

C

C, I

I

C

I

C

C, I

I

C

I

Notes:

1. C = Commercial, I = Industrial

2. -5 speed grade for MACH111 (SP) = 5.0 ns tPD

3. -5 speed grade for MACH131(SP) = 5.5 ns tPD

The MACH 1 & 2 families consist of ten devices—five base options, each with a counterpart that

includes JTAG-compatible in-system programming (ISP). These devices offer five different density-

I/O combinations in Thin Quad Flat Pack (TQFP), Plastic Quad Flat Pack (PQFP), and Plastic

Leaded Chip Carrier (PLCC) packages from 44 to 100 pins (Table 3). Each MACH 1 & 2 device is

PCI compliant and includes other features such as SpeedLocking architecture for guaranteed fixed

timing, Bus-Friendly inputs and I/Os, and programmable power-down mode for extra power

savings.

2

MACH 1 & 2 Families

Share Link: