MACH211SP-10VC データシートの表示（PDF） - Lattice Semiconductor

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MACH211SP-10VC

High-Performance EE CMOS Programmable Logic

Lattice Semiconductor 

FUNCTIONAL DESCRIPTION

Each MACH 1 and 2 device consists of multiple, optimized PAL® blocks interconnected by a switch

matrix. The switch matrix allows communication between PAL blocks, and routes inputs to the PAL

blocks. Together, the PAL blocks and switch matrix allow the logic designer to create large designs

in a single device instead of using multiple devices.

Clock/Input Pins

I/O Pins

PAL Block

Array and

Allocator

Output

Macrocells

Buried

Macrocells

Buried Macrocell Feedback

Output Macrocell Feedback

I/O Pin Feedback

(note 1)

I/O Cells

I/O Pins

PAL Block

I/O Pins

PAL Block

PAL Block

I/O Pins

Note:

Dedicated Input

1. There are no buried macrocells in MACH 1 devices. All macrocells are output macrocells.

Device

MACH111(SP)

MACH131(SP)

MACH211(SP)

MACH221(SP)

MACH231(SP)

PAL Blocks

2

4

4

8

8

Macrocells per Block

16

16

16

12

16

I/Os per Block

16

16

8

6

8

14051K-002

Product Terms per Block

70

70

68

52

68

Figure 1. Overall Architecture of MACH 1 & 2 Devices

The switch matrix takes all dedicated inputs and signals from the input switch matrices and routes

them as needed to the PAL blocks. Feedback signals that return to the same PAL block still must

go through the switch matrix. This mechanism ensures that PAL blocks in MACH devices

communicate with each other with guaranteed fixed timing (SpeedLocking).

The switch matrix makes a MACH device more advanced than simply several PAL devices on a

single chip. It allows the designer to think of the device not as a collection of blocks, but as a

single programmable device; the software partitions the design into PAL blocks through the

central switch matrix so that the designer does not have to be concerned with the internal

architecture of the device.

4

MACH 1 & 2 Families

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