MACH211SP-10VC データシートの表示（PDF） - Lattice Semiconductor

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MACH211SP-10VC

High-Performance EE CMOS Programmable Logic

Lattice Semiconductor 

The output macrocell (Figure 3) sends its output back to the switch matrix, via internal feedback,

and to the I/O cell. The feedback is always available regardless of the configuration of the I/O cell.

This allows for buried combinatorial or registered functions, freeing up the I/O pins for use as

inputs if not needed as outputs. The basic output macrocell configurations are shown in Figure 4.

The buried macrocell (Figure 5) does not send its output to an I/O cell. The output of a buried

macrocell is provided only as an internal feedback signal which feeds the switch matrix. This

allows the designer to generate additional logic without requiring additional pins. The buried

macrocell can also be used to register or latch inputs. The input register is a D-type flip-flop; the

input latch is a transparent-low D-type latch. Once configured as a registered or latched input, the

buried macrocell cannot generate logic from the product-term array. The basic buried macrocell

configurations are shown in Figure 6.

PAL-Block

Asynchronous

Preset

Sum of Products

from Logic

Allocator

CLK0

CLKn

PAL-Block

Asynchronous

Reset

To

Switch

Matrix

Note:

1. Latch option available on MACH 2 devices only.

1

AP

D/T/L1 Q

0

AR

1

To I/O

0

Cell

14051K-004

Figure 3. Output Macrocell

8

MACH 1 & 2 Families

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