ATF2500C(2003) データシートの表示（PDF） - Atmel Corporation
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ATF2500C Datasheet PDF : 20 Pages
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Description
Using the
ATF2500C
Family’s Many
Advanced
Features
The ATF2500C is the highest-density PLD available in a 44-pin package. With its fully con-
nected logic array and flexible macrocell structure, high gate utilization is easily obtainable.
The ATF2500C is a high-performance CMOS (electrically-erasable) programmable logic
device (PLD) that utilizes Atmel’s proven electrically-erasable technology.
The ATF2500C is organized around a single universal array. All pins and feedback terms are
always available to every macrocell. Each of the 38 logic pins are array inputs, as are the out-
puts of each flip-flop.
In the ATF2500C, four product terms are input to each sum term. Furthermore, each macro-
cell’s three sum terms can be combined to provide up to 12 product terms per sum term with
no performance penalty. Each flip-flop is individually selectable to be either D- or T-type, pro-
viding further logic compaction. Also, 24 of the flip-flops may be bypassed to provide internal
combinatorial feedback to the logic array.
Product terms provide individual clocks and asynchronous resets for each flip-flop. The flip-
flops may also be individually configured to have direct input pin clocking. Each output has its
own enable product term. Eight synchronous preset product terms serve local groups of either
four or eight flip-flops. Register preload functions are provided to simplify testing. All registers
automatically reset upon power-up.
The ATF2500Cs advanced flexibility packs more usable gates into 44 leads than other PLDs.
Some of the ATF2500Cs key features are:
• Fully Connected Logic Array – Each array input is always available to every product
term. This makes logic placement a breeze.
• Selectable D- and T-Type Registers – Each ATF2500C flip-flop can be individually
configured as either D- or T-type. Using the T-type configuration, JK and SR flip-flops are
also easily created. These options allow more efficient product term usage.
• Buried Combinatorial Feedback – Each macrocell’s Q2 register may be bypassed to
feed its input (D/T2) directly back to the logic array. This provides further logic expansion
capability without using precious pin resources.
• Selectable Synchronous/Asynchronous Clocking – Each of the ATF2500Cs flip-flops
has a dedicated clock product term. This removes the constraint that all registers use the
same clock. Buried state machines, counters and registers can all coexist in one device
while running on separate clocks. Individual flip-flop clock source selection further allows
mixing higher performance pin clocking and flexible product term clocking within one
design.
• A Total of 48 Registers – The ATF2500C provides two flip-flops per macrocell – a total of
48. Each register has its own clock and reset terms, as well as its own sum term.
• Independent I/O Pin and Feedback Paths – Each I/O pin on the ATF2500C has a
dedicated input path. Each of the 48 registers has its own feedback term into the array as
well. These features, combined with individual product terms for each I/O’s output enable,
facilitate true bi-directional I/O design.
• Combinable Sum Terms – Each output macrocell’s three sum terms may be combined
into a single term. This provides a fan in of up to 12 product terms per sum term with no
speed penalty.
• Programmable Pin-keeper Circuits – These weak feedback latches are useful for bus
interfacing applications. Floating pins can be set to a known state if the Pin-keepers are
enabled.
• User Row (64 bits) – Use to store information such as unit history.
2 ATF2500C Family
0777I–PLD–4/03
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