ATF2500C データシートの表示（PDF） - Atmel Corporation

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ATF2500C

ATF2500C CPLD Family Datasheet

Atmel Corporation 

ATF2500C

3. Using the ATF2500C Family’s Many Advanced Features

The ATF2500Cs advanced flexibility packs more usable gates into 44 leads than other PLDs.

Some of the ATF2500Cs key features are:

• Fully Connected Logic Array – Each array input is always available to every product term.

This makes logic placement a breeze.

• Selectable D- and T-Type Registers – Each ATF2500C flip-flop can be individually

configured as either D- or T-type. Using the T-type configuration, JK and SR flip-flops are also

easily created. These options allow more efficient product term usage.

• Buried Combinatorial Feedback – Each macrocell’s Q2 register may be bypassed to feed

its input (D/T2) directly back to the logic array. This provides further logic expansion capability

without using precious pin resources.

• Selectable Synchronous/Asynchronous Clocking – Each of the ATF2500Cs flip-flops has

a dedicated clock product term. This removes the constraint that all registers use the same

clock. Buried state machines, counters and registers can all coexist in one device while

running on separate clocks. Individual flip-flop clock source selection further allows mixing

higher performance pin clocking and flexible product term clocking within one design.

• A Total of 48 Registers – The ATF2500C provides two flip-flops per macrocell – a total of 48.

Each register has its own clock and reset terms, as well as its own sum term.

• Independent I/O Pin and Feedback Paths – Each I/O pin on the ATF2500C has a dedicated

input path. Each of the 48 registers has its own feedback term into the array as well. These

features, combined with individual product terms for each I/O’s output enable, facilitate true

bi-directional I/O design.

• Combinable Sum Terms – Each output macrocell’s three sum terms may be combined into

a single term. This provides a fan in of up to 12 product terms per sum term with no speed

penalty.

• Programmable Pin-keeper Circuits – These weak feedback latches are useful for bus

interfacing applications. Floating pins can be set to a known state if the Pin-keepers are

enabled.

• User Row (64 bits) – Use to store information such as unit history.

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0777K–PLD–1/24/08

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