ATF2500C データシートの表示（PDF） - Atmel Corporation
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ATF2500C Datasheet PDF : 24 Pages
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ATF2500C
5. Preload and Observability of Registered Outputs
The ATF2500Cs registers are provided with circuitry to allow loading of each register asynchro-
nously with either a high or a low. This feature will simplify testing since any state can be forced
into the registers to control test sequencing. A VIH level on the odd I/O pins will force the appro-
priate register high; a VIL will force it low, independent of the polarity or other configuration bit
settings.
The PRELOAD state is entered by placing an 10.25V to 10.75V signal on SMP lead 42. When
the preload clock SMP lead 23 is pulsed high, the data on the I/O pins is placed into the 12 reg-
isters chosen by the Q select and even/odd select pins.
Register 2 observability mode is entered by placing an 10.25V to 10.75V signal on pin/lead 2. In
this mode, the contents of the buried register bank will appear on the associated outputs when
the OE control signals are active.
Figure 5-1. Preload Waveforms
Table 5-1. Preload Levels
Level Forced on Odd
I/O Pin during
PRELOAD Cycle
Q Select
Pin State
VIH/VIL
VIH/VIL
VIH/VIL
VIH/VIL
Low
High
Low
High
Even/Odd
Select
Low
Low
High
High
Even Q1
State after
Cycle
High/Low
X
X
X
Even Q2
State after
Cycle
X
High/Low
X
X
Odd Q1
State after
Cycle
X
X
High/Low
X
Odd Q2
State after
Cycle
X
X
X
High/Low
5
0777K–PLD–1/24/08
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