IDT54821BTP データシートの表示（PDF） - Integrated Device Technology
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IDT54821BTP Datasheet PDF : 9 Pages
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IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT821/823/825AT
FCT821/823/825BT
Symbol
tPLH
tPHL
Parameter
Propagation Delay
CP to YI (OE = LOW)
tSU
tH
tSU
tH
tPHL
Set-up Time HIGH or LOW
DI to CP
Hold Time HIGH or LOW
DI to CP
Set-up Time HIGH or LOW
EN to CP
Hold Time HIGH or LOW
EN to CP
Propagation Delay, CLR to YI
Condition(1)
CL = 50pF
RL = 500Ω
CL = 300pF(4)
RL = 500Ω
CL = 50pF
RL = 500Ω
Com'l.
Min.(2) Max.
1.5 10.0
Mil.
Min.(2) Max.
1.5 11.5
Com'l.
Min.(2) Max.
1.5 7.5
Mil.
Min.(2) Max.
1.5 8.5
Unit
ns
1.5 20.0 1.5 20.0 1.5 15.0 1.5 16.0
4.0 — 4.0 — 3.0 — 3.0 — ns
2.0 — 2.0 — 1.5 — 1.5 — ns
4.0 — 4.0 — 3.0 — 3.0 — ns
2.0 — 2.0 —
0
—
0
— ns
1.5 14.0 1.5 15.0 1.5 9.0 1.5 9.5 ns
tREM
Recovery Time CLR to CP
6.0 — 7.0 — 6.0 — 6.0 — ns
tW
Clock Pulse Width
HIGH or LOW
7.0 — 7.0 — 6.0 — 6.0 — ns
tW
CLR Pulse Width LOW
6.0 — 7.0 — 6.0 — 6.0 — ns
tPZH
Output Enable Time OE to YI
CL = 50pF
1.5 12.0 1.5 13.0 1.5 8.0 1.5 9.0 ns
tPZL
RL = 500Ω
CL = 300pF(4)
1.5 23.0 1.5 25.0 1.5 15.0 1.5 16.0
RL = 500Ω
tPHZ
Output Disable Time OE to Y I
CL = 5pF(4)
1.5 7.0 1.5 8.0 1.5 6.5 1.5 7.0 ns
tPLZ
RL = 500Ω
CL = 50pF
1.5 8.0 1.5 9.0 1.5 7.5 1.5 8.0
RL = 500Ω
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
4. This condition is guaranteed but not tested.
2567 tbl 08
6.21
6
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