LC72720YV(2013) データシートの表示（PDF） - ON Semiconductor
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LC72720YV Datasheet PDF : 18 Pages
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Item
PT2 = 0
PT2 = 1
Mode2 (PT2 = 0)
No SK
SK present
LC72720YV
Pin T3 (RDCL)
Data(RDDA and RSFT) changes on this pin’s rising edge
Data(RDDA and RSFT) changes on this pin’s falling edge
Pin T7 (ARI-ID)
High (1)
Low (0)
Mode3 (PT2 = 0)
Correction not possible
Errors corrected
No errors
Pin T6 (ERROR)
Low (0)
High (1)
High (1)
Pin T7 (CORREC)
Low (0)
Low (0)
High (1)
Mode = 4
Number of error blocks (B)
Pin T6 (BE1)
Pin T7 (BE0)
B=0
Low (0)
Low (0)
1 ≤ B ≤ 20
Low (0)
High (1)
20 < B ≤ 40
High (1)
Low (0)
40 < B ≤ 48
High (1)
High (1)
These pins indicate the number of blocks in a set of 48 blocks that had errors before correction.
The output polarity of these pins is fixed at the values listed in the table.
Mode (PT2 = 0)
The SYNC pin
0 to 2
When synchronized : Low (0), When unsynchronized: High (1)
When synchronized : Goes high for a fixed period (421 μs) at the
3
start of a block and then goes low.
When unsynchronized : High (1)
Caution : The output indicates the synchronization state for the previous block.
When PT2 = 0
No RDS
RDS present
The RDS-ID pin
High (1)
Low (0)
(10) Test mode settings (4bits) : TS0 to TS3
Initial values : TS0 = 0, TS1 = 0, TS2 = 0, TS3 = 0
(Applications must set these bits to the above values.)
Notes : The T1 and T2 pins (pins 9 and 10) are related to test mode as follows.
Pin T1 Pin T2
IC operation
0
0
Normal operating mode
0
1
Standby mode (crystal oscillator stopped)
1
0/1
The T1 pin must be tied to VSS (0V).
IC test mode
(11) Circuit control (2 bits) : CT0 and CT1
Notes
These states are user settable
Users cannot use this state
Item
CT0
RSFT control
CT1
RDS-ID detection condition
Initial value : CT0 = 0, CT1 = 0
Control
When set to 1, soft-decision control data (RSFT) is
easier to generate.
When set to 1, the RDS-ID detection conditions are
made more restrictive.
No. 6488-12/18
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