ISPLSI5384VE-80LF256 データシートの表示（PDF） - Lattice Semiconductor
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ISPLSI5384VE-80LF256 Datasheet PDF : 22 Pages
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Specifications ispLSI 5384VE
ispLSI 5384VE Timing Parameters (continued)
ADDER
ADDER TYPE BASE PARAMETER
-165
-125
-100
-80
UNITS
Routing Adders
tlp
troute
1.0
1.5
1.5
1.5
ns
Tioi Input Adders
clk1
clk2
clk3
tgclk_in
tgclk_in
tgclk_in
1.4
1.7
1.7
1.7
ns
1.4
1.7
1.7
1.7
ns
1.4
1.7
1.7
1.7
ns
Tioo Output Adders1
Slow Slew I/O
tbuf, ten
4.0
4.0
4.0
4.0
ns
LVTTL_out
tbuf, ten, tdis
0.0
0.0
0.0
0.0
ns
LVCMOS25_out
tbuf, ten, tdis
0.5
0.5
0.5
0.5
ns
LVCMOS33_out
tbuf, ten, tdis
0.0
0.0
0.0
0.0
ns
Tbla Additional Block Loading Adders
1
troute
0.1
0.1
0.1
0.1
ns
2
troute
0.1
0.2
0.2
0.2
ns
3
troute
0.2
0.3
0.3
0.3
ns
4
troute
0.3
0.4
0.4
0.4
ns
5
troute
0.4
0.5
0.5
0.5
ns
6
troute
0.4
0.6
0.6
0.6
ns
7
troute
0.5
0.7
0.7
0.7
ns
8
troute
0.6
0.8
0.8
0.8
ns
9
troute
0.6
0.9
0.9
0.9
ns
10
troute
0.7
1.0
1.0
1.0
ns
11
troute
0.8
1.1
1.1
1.1
ns
1Timing for open drain configurations is the same as non-open drain configurations.
Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for
details.
Timing Table/5384VE
Timing v.2.0
16
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