TDA8020HL/C1,118 データシートの表示（PDF） - NXP Semiconductors.
部品番号
コンポーネント説明
メーカー
TDA8020HL/C1,118 Datasheet PDF : 28 Pages
| |||
Philips Semiconductors
Dual IC card interface
Product specification
TDA8020HL
called the master. The devices that are controlled by the
master are called slaves.
Each byte is followed by one HIGH-level acknowledge bit
asserted by the transmitter. The master generates an
extra acknowledge related clock pulse. The slave receiver
which is addressed is obliged to generate an acknowledge
after the reception of each byte.
The master receiver must generate an acknowledge after
the reception of each byte that has been clocked out of the
slave transmitter.
The device that acknowledges has to pull-down the SDA
line during the acknowledge clock pulse in such a way that
the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse.
Set-up and hold times must be taken into account.
A master receiver must signal an end of data to the slave
transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this event,
the transmitter must leave the data line HIGH to enable the
master generation of the STOP condition.
See Chapter “Characteristics” for timing information.
DEVICE ADDRESSING
Each device has 2 different addresses, one for each card.
An application can use up to four devices in parallel by the
use of address selection pins SAD0 and SAD1.
Pins SAD0 and SAD1 are externally hardwired to VDD or
GND; SAD0 specifies address bit A0, SAD1 specifies
address bit A1; Address bit R/W specifies either read or
write operation: logic 1 = Read, logic 0 = Write (see
Tables 1 and 2).
Table 1 Proposed device address bit allocations
Device
7
6
5
TDA8020HL
0
1
0
Address bits
4
3
2
0
0/1
A1
1
0
A0
R/W
Table 2 Proposed I2C-bus addresses for 4 devices in parallel
PIN SAD1
LOW
LOW
HIGH
HIGH
PIN SAD0
LOW
HIGH
LOW
HIGH
CARD 1
40H
42H
44H
46H
CARD 2
48H
4AH
4CH
4EH
2003 Nov 06
9
Share Link: 