MB40C328PFV データシートの表示（PDF） - Fujitsu

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MB40C328PFV

8-bit 100 MSPS A/D Converter

Fujitsu 

MB40C328

s TIMING CHART 1

CLK input-straight output mode

• CLK = 100 MHz (max)

• CLKA = CLKB = “L” (DVSS)

• CKSEL = “H” (AVDD)

• DSEL = “H” (DVDD)

• RESET = “H” (DVDD)

• CE = “L” (AVSS)

• OE = “L” (DVSS)

VIHD

CLK input

VIHD

tr

N−1

N

tf

DVDDI − 0.5 V

0.5 V

N+1

N+2

VINA input

tAD

N+3

N+4

VOHD

DA0 to DA7

VOLD

N−7

VOHD

DB0 to DB7

VOLD

VOHD

CLKOA

VOLD

VOHD

CLKOB

VOLD

N−6

N−5

N−4

N−3

N−2

ALL “L” fix

ALL “L” fix

tWS+ tWS−

N+5

N+6

1.5 V

N+7

tpdS (max)

tpdS (typ)

tpdS (min)

N

N−1

DVDD − 0.4 V

0.4 V

N+1

tpdSO(max)

tpdSO(typ)

tpdSO(min)

DVDD − 0.4 V

0.4 V

• VINA input — Sampling at CLK rising

• DA0 to DA7 — Output (after 5 CLK + tpdS from Sampling) at CLK rising

9

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