TB62705CFGEL データシートの表示（PDF） - Toshiba

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TB62705CFGEL

TOSHIBA Bi−CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC

Toshiba 

BLOCK DIAGRAM

OUTn

OUTn

TB62705CPG/CFG/CFNG

OUTn

TIMING DIAGRAM

CLOCK

5V

0V

SERIAL-IN

5V

0V

LATCH

5V

0V

ENABLE

5V

0V

OUT0

Off

On

OUT1

Off

On

OUT3

Off

On

OUT7

Off

5V

SERIAL-OUT

0V

Note:

Latches are level-sensitive, not rising edge-sensitive, and are not synchronized with the CLOCK signal. The

data will pass through the latch circuit if the latch input is set at “H” level, and will be retained if the input is

set at “L”.

2

2005-10-06

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