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SPT7755A データシートの表示(PDF) - Signal Processing Technologies

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SPT7755A
SPT
Signal Processing Technologies SPT
SPT7755A Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
GENERAL DESCRIPTION
The SPT7755 is one of the fastest monolithic 8-bit parallel
flash A/D converters available today. The nominal conver-
sion rate is 750 MSPS and the analog bandwidth is in excess
of 900 MHz. A major advance over previous flash converters
is the inclusion of 256 input preamplifiers between the
reference ladder and input comparators (see block dia-
gram). This not only reduces clock transient kickback to the
input and reference ladder due to a low AC beta but also
reduces the effect of the dynamic state of the input signal on
the latching characteristics of the input comparators. The
preamplifiers act as buffers and stabilize the input capaci-
tance so that it remains constant over different input voltage
and frequency ranges and therefore makes the part easier to
drive than previous flash converters. The preamplifiers also
add a gain of two to the input signal so that each comparator
has a wider overdrive or threshold range to "trip" into or out
of the active state. This gain reduces metastable states that
can cause errors at the output.
The SPT7755 has true differential analog and digital data
paths from the preamplifiers to the output buffers (Current
Mode Logic) for reducing potential missing codes while
rejecting common mode noise.
Signature errors are also reduced by careful layout of the
analog circuitry. The output drive capability of the device can
provide full ECL swings into 50 loads.
Figure 1 - SPT7755 Typical Interface Circuit
VIN**
VIN
50
VIN
VRTF
R
VRTS
R
-2.0 V
Reference
+
22
- U1
VRM
*
-
22 2N2907
+U1
*
VRBS
VRBF
-5.2 V
-5.2 V
DRB (DATA READY)
DRB (DATA READY)
D8B (OVR)
D7B (MSB)
D6B
D5B
D4B
D3B
D2B
D1B
D0B (LSB)
DRA (DATA READY)
DRA (DATA READY)
D8A (OVR)
D7A (MSB)
D6A
D5A
D4A
D3A
D2A
D1A
D0A (LSB)
Convert
U2
50
50
CLK
NCLK
-2 V
Pulldown
(Analog)
* FB
-5.2 V
.1 µF
-2.0 V
Pulldown
(Digital)
FB= Ferrite bead
U1= OP291 or equivalent with low offset/noise.
R = 1 k ; 0.1% matched.
= AGND
= DGND
U2= Motorola ECLinPS Lite, MC10EL16, differential receiver
with 250 ps (typ) propagation delay.
* = 10 µF Tantalum Capacitor and 0.1 µF Chip Capacitor
** = Care must be taken to avoid exceeding the maximum rating
for the input, especially during power up sequencing of the
analog input driver.
SPT
4
SPT7755
3/5/97

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