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LC99052-V64A データシートの表示(PDF) - SANYO -> Panasonic

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LC99052-V64A
SANYO
SANYO -> Panasonic SANYO
LC99052-V64A Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
Pin Functions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Symbol
VDD1 (AMOS-A)
CCDIN
CAP1
AMPIN
CLAMPDC
GOUT
GAININ
AMPOUT
CAPA2
YOUT
YIN
CAPB2
TOAMPDC
VSS1 (AMOS-A)
VDD2 (ADC-A)
REFHIN
REFLIN
REFH
REFM
REFL
VSS2 (ADC-A)
VSS3 (ADC-D)
VDD3 (ADC-D)
24
EXT1
25
EXT2
26
EXT3
27
EXT4
28
CLKS
29
DATAS
30
REGRESB
31
HR
32
VR
33
FTTRG
34
STTRG
35
CSYNC
36
HD
37
VD
38
FLD
39
IREF1
40
VSS6 (DATA)
41
VDD6 (DATA)
42
IREF2
43
VREFIN
44
VDD5 (DAC-A)
45
VSS5 (DAC-A)
46
VIDEO
47
COMP
48
IREFOUT
49
VSS4 (DAC-D)
50
VDD4 (DAC-D)
LC99052-V64A
I/O I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: Unconnected pin
I/O
Function
I CCD input pin
I AMOS-CDS bias pin
I 6 dB amplifier input pin
O 6 dB amplifier clamp circuit bias output pin
O Gain control output
I Gain control input
O 6 dB amplifier output pin
I AMOS-AGC bias pin
O AGC output
I Clamp, A/D converter input
I AMOS-clamp bias pin
O 6 dB amplifier bias output pin
I A/D converter high level reference input
I A/D converter low level reference input
O A/D converter high level reference output
O A/D converter middle level reference output
O A/D converter low level reference output
EXT1, 2 = 00: Direct H and V reset, 10: Direct C.sync reset
01: Mode 3, an external clamp pulse can be input from pin 32 (VR), ENDFLG is output from
I
pin 36 (CSYNC).
11: NON
I
I EXT3, 4 = 00: Auto iris, 10: Normal, 01: External shutter, 11: External FT, ST
I
I Serial clock input
I Serial data input
I Register reset; 0: Reset
I Hsync, CSYNC reset pulse input
I Vsync reset pulse input
External frame_sift trigger input
I
Auto iris mode = selmet1
External shutter trigger input
I
Auto iris mode = selmet2
In mode 3 (H reset mode), this pin outputs ENDFLG.
O This pin is affected by the SSG_DELAY (register).
O This pin is affected by the SSG_DELAY (register).
O This pin is affected by the SSG_DELAY (register).
This pin is affected by the SSG_DELAY (register). Outputs a video output frame index pulse in long
O exposure mode.
I Automatic iris and AGC hold; 1: Hold, 0: Active
I Automatic iris fine adjustment; 1: Bright, 0: Normal
I D/A converter reference voltage input
O D/A converter output (video output)
O D/A converter bias pin
O D/A converter reference voltage output
Continued on next page.
No. 5072-3/8

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