LC99052-V64A データシートの表示（PDF） - SANYO -> Panasonic

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LC99052-V64A

Image Sensor Control LSI

SANYO -> Panasonic 

LC99052-V64A

Main Functions Provided by the LC99052-V64A

1. SSG

• Handles both the NTSC and PAL formats.

• The NTSC reference clock is 8Fsc = 28.63636 MHz.

• The PAL reference clock is 28.375 MHz.

However, the LC99052-V64A does not generate a 4Fsc clock. 4Fsc is not required when an LC99062-W50 is

used.

• The SSG delay with respect to the TG phase can be set to an arbitrary value to compensate for the delay in the

digital signal processing connected to the last stage.

• Handles external synchronization. Includes a sync separator circuit that separates HSYNC and VSYNC from

C.SYNC.

2. TG

• Generates all pulses required to drive Sanyo CCD products (LC9947G/48G/97G/98G).

• Supports interlaced and non-interlaced drive.

• Handles long exposure drive (1 V to 16 V).

• External exposure time control can be implemented easily.

3. Electronic Iris

• Incorporates, as digital circuits, all circuits required for electronic iris (exposure control using an electronic shutter

function), including video signal integration, detector, and exposure control circuits. Allows stabilized control.

• Response speed and rate are settable.

• Five light metering patterns are supported.

— Full-screen light metering, center area light metering, lower-side light metering

— Center-weighted metering with three areas measured

— Lower-side-weighted metering with three areas measured

• Handles long exposure times.

4. CDS (coefficient dual-sampling circuit)

• Hold capacitor built in

• Adjustment-free

5. AGC Amplifier Circuit

• Adjustment-free

• The AGC control signals are generated by a digital control system linked to the electronic iris and a built-in 10-bit

D/A converter. The gain can be set with digital codes.

• The gain variability is 10 dB. The maximum gain is about 20 dB when the built-in 6 dB amplifier is not used.

6. A/D Converter

• After CDS, AGC, and OPB clamp processing has been applied to the CCD imaged signal, the A/D converter

converts that signal to an 8-bit digital signal.

• Built-in OPB clamp circuit in the front end.

• Built-in operational amplifier for reference voltage generation. The reference voltage can be resistor divided to

provide any required voltage. Note that black level adjustment is not required since the same voltage is used as the

reference voltage and as the front end clamp circuit bias voltage.

7. Line Memory

• Mirror processing (left-to-right reversal) is supported by setting a single external pin.

• The digital image output can be freely delayed with respect to the CCD drive. This function allows the 8-bit D/A

converter output timing to be set to the same phase as the CCD drive to prevent pulse interference in the video

period without affecting the external digital signal processing delay time.

No. 5072-7/8

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