ISPLSI3256A-70LQ データシートの表示（PDF） - Lattice Semiconductor
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ISPLSI3256A-70LQ Datasheet PDF : 13 Pages
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Specifications ispLSI 3256A
Pin Description
NAME
I/O 0 - I/O 4
I/O 5 - I/O 9
I/O 10 - I/O 14
I/O 15 - I/O 19
I/O 20 - I/O 24
I/O 25 - I/O 29
I/O 30 - I/O 34
I/O 35 - I/O 39
I/O 40 - I/O 44
I/O 45 - I/O 49
I/O 50 - I/O 54
I/O 55 - I/O 59
I/O 60 - I/O 64
I/O 65 - I/O 69
I/O 70 - I/O 74
I/O 75 - I/O 79
I/O 80 - I/O 84
I/O 85 - I/O 89
I/O 90 - I/O 94
I/O 95 - I/O 99
I/O 100 - I/O 104
I/O 105 - I/O 109
I/O 110 - I/O 114
I/O 115 - I/O 119
I/O 120 - I/O 124
I/O 125 - I/O 127
GOE0 and GOE1
TOE
RESET
Y0, Y1 and Y2
Y3 and Y4
BSCAN/ispEN
TDI/SDI
TCK/SCLK
TMS/MODE
TRST
TDO/SDO
GND
VCC
PQFP/MQFP PIN NUMBERS
25, 26,
28, 29,
30,
32, 33,
34, 35,
36,
37, 38,
39, 40,
41,
42, 43,
44, 46,
47,
48, 49,
50, 52,
53,
54, 55,
56, 57,
58,
59, 60,
61, 62,
64,
65, 66,
67, 68,
69,
70, 72,
73, 74,
75,
76, 77,
78, 79,
80,
82, 83,
84, 85,
86,
87, 88,
89, 90,
92,
93, 94,
95, 96,
105,
106, 108, 109, 110, 112,
113, 114, 115, 116, 117,
118, 119, 120, 121, 122,
123, 124, 126, 127, 128,
129, 130, 132, 133, 134,
135, 136, 137, 138, 139,
140, 141, 142, 144, 145,
146, 147, 148, 149, 150,
152, 153, 154, 155, 156,
157, 158, 159, 160, 2,
3, 4,
5,
6,
7,
8, 9,
11, 13,
14,
15, 16, 17
100 and 99
98
20
18, 19, 103
102, 101
21
22
23
24
97
104
1,
10,
27, 45,
63,
81, 107, 125, 143
12, 31,
51, 71,
91,
111, 131, 151
DESCRIPTION
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
Global Output Enable input pins.
Test output enable pin - This pin tristates all I/O pins when a logic low is
driven
Active Low (0) Reset pin which resets all of the GLB and I/O registers in
the device.
Dedicated Clock inputs. These clock inputs are connected to one of the
clock inputs of all the GLBs on the device.
Dedicated Clock inputs. These clock inputs are connected to one of the
clock inputs of all the I/O cells in the device.
Input – Dedicated in-system programming enable input pin. When this pin is high,
the BSCAN TAP controller pins TMS, TDI, TDO and TCK are enabled. When this
pin is brought low, the ISP state machine control pins MODE, SDI, SDO and
SLCK are enabled. High-to-low transition of this pin will put the device in the
programming mode and put all I/O pins in high-Z state.
Input – This pin performs two functions depending on the state of the
BSCAN/ispEN pin. It is the Test Data input to the TAP Controller when the ispEN
is logic high. TDI is used to load BSCAN test data or programming data. When
ispEN is logic low, it functions as an input pin to load programming data into the
ISP state machine.
Input – This pin performs two functions, depending on the state of the
BSCAN/ispEN pin. It is the Test Clock input pin when BSCAN/ispEN is logic high.
When BSCAN/ispEN is logic low, it functions as the clock for the ISP state
machine.
Input – This pin performs two functions, depending on the state of the
BSCAN/ispEN pin. It is the Test Mode Select input pin when BSCAN/ispEN is
logic high. When BSCAN/ispEN is logic low, it functions to control the operation of
the ISP state machine.
Input – Test Reset, active low to reset the Boundary Scan state machine.
Output – This pin performs two functions, depending on the state of the
BSCAN/ispEN pin. It is the Test Data Output pin when BSCAN/ispEN is logic high,
and either BSCAN test data or programming data is shifted out. When
BSCAN/ispEN is logic low, it is the Serial Data Output of the ISP state machine.
Ground (GND)
VCC
Table 2-0002/3256A.a
11
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