ISPLSI3256A-70LQ データシートの表示（PDF） - Lattice Semiconductor

部品番号

コンポーネント説明

メーカー

ISPLSI3256A-70LQ

In-System Programmable High Density PLD

Lattice Semiconductor 

Specifications ispLSI 3256A

ispLSI 3256A Timing Model

I/O Cell

GRP

I/O Pin

(Input)

#52

I/O Reg Bypass

#24

Input

D Register Q

RST

#25 - 29

Reset

Y3,4

#51

GRP

#30

GLB

Feedback

4 PT Bypass

#32

20 PT

XOR Delays

#33 - 35

#52

#31

GLB Reg Bypass

#36

GLB Reg

Delay

D

Q

RST

#37 - 40

ORP

ORP Bypass

#45

ORP

Delay

#44

Control RE

PTs OE

#41 - 43 CK

#50

Y0,1,2

GOE0,1

#53

TOE

#54

0902/3256A

Derivations of tsu, th and tco from the Product Term Clock1

tsu

= Logic + Reg su - Clock (min)

= (tiobp + tgrp + t20ptxor) + (tgsu) - (tiobp + tgrp + tptck(min))

= (#24+ #30+ #34) + (#37) - (#24+ #30+ #43)

4.6 ns = (1.9 + 2.4 + 6.4) + (1.0) - (1.9 + 2.4 + 2.8)

th

= Clock (max) + Reg h - Logic

= (tiobp + tgrp + tptck(max)) + (tgh) - (tiobp + tgrp + t20ptxor)

= (#24+ #30+ #43) + (#38) - (#24+ #30+ #34)

3.7 ns = (1.9 + 2.4 + 5.3) + (4.8) - (1.9 + 2.4 + 6.4)

tco

= Clock (max) + Reg co + Output

= (tiobp + tgrp + tptck(max)) + (tgco) + (torp + tob)

= (#24 + #30 + #43) + (#39) + (#44 + #46)

15.4 ns = (1.9 + 2.4 + 5.3) + (1.6) + (2.3 + 1.9)

Table 2-0042/3256A

Note: Calculations are based on timing specs for the ispLSI 3256A-90L.

I/O Cell

#46, 47

I/O Pin

(Output)

#48, 49

9

Share Link: