5962-9461403HXX データシートの表示（PDF） - White Electronic Designs Corporation
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5962-9461403HXX Datasheet PDF : 13 Pages
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White Electronic Designs
WE32K32-XXX
FIGURE 10 –
SOFTWARE BLOCK DATA PROTECTION
DISABLE ALGORITHM(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 20
TO
ADDRESS 5555
LOAD DATA XX
TO
ANY ADDRESS(4)
LOAD LAST BYTE
TO
LAST ADDRESS
EXIT DATA
PROTECT STATE(3)
NOTES:
1. Data Format: I/O15-0 (Hex);
Address Format: A16 -A0 (Hex).
2. Write Protect state will be activated at end of write even if no other
data is loaded.
3. Write Protect state will be deactivated at end of write period even if
no other data is loaded.
4. 1 to 64 bytes of data may loaded.
SOFTWARE DATA PROTECTION
A software write protection feature may be enabled
or disabled by the user. When shipped by White
Microelectronics, the WE32K32-XXX has the feature
disabled. Write access to the device is unrestricted.
To enable software write protection, the user writes three
access code bytes to three special internal locations.
Once write protection has been enabled, each write to the
EEPROM must use the same three byte write sequence
to permit writing. After setting software data protection,
any attempt to write to the device without the three-byte
command sequence will start the internal write timers. No
data will be written to the device, however, for the duration
of tWC. The write protection feature can be disabled by
a six byte write sequence of specific data to specific
locations. Power transitions will not reset the software
write protection.
Each 32KByte block of the EEPROM has independent write
protection. One or more blocks may be enabled and the rest
disabled in any combination. The software write protection
guards against inadvertent writes during power transitions,
or unauthorized modification using a PROM programmer.
HARDWARE DATA PROTECTION
These features protect against inadvertent writes to the
WE32K32-XXX. These are included to improve reliability
during normal operation:
a) VCC power on delay
As VCC climbs past 3.8V typical the device will wait
5msec typical before allowing write cycles.
b) VCC sense
While below 3.8V typical write cycles are inhibited.
c) Write inhibiting
Holding OE# low and either CS# or WE# high
inhibits write cycles.
d) Noise filter
Pulses of <8ns (typ) on WE# or CS# will not initiate
a write cycle.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 4
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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