S87L51FB-8A44 データシートの表示（PDF） - Philips Electronics
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S87L51FB-8A44 Datasheet PDF : 16 Pages
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Philips Semiconductors
CMOS single-chip 3.0V 8-bit microcontrollers
Product specification
87L51FA/87L51FB
PROGRAMMABLE COUNTER ARRAY
The PCA is a sophisticated free-running 16 bit Timer/Counter that
drives 5 modules that can be individually configured as Capture
inputs, software timers, high speed outputs, or pulse width
modulated outputs. In addition, module 4 can be configured as a
software controlled watchdog timer.
The Timer portion of the PCA can be configured to run in one of four
different modes. The modes are: 1/2 the oscillator frequency, 1/4 the
oscillator frequency, Timer 0 overflows, or from the ECI input.
For the Capture/Compare mode each of the modules has a pair of
registers associated with it called CCAPnH and CCAPnL (where
n = 0, 1, 2, 3, 4 depending on the module). Both positive and
negative transitions can be captured. This means that the PCA has
the flexibility to measure phase differences, duty cycles, pulse
widths and a wide variety of other digital pulse characteristics.
In the 16-bit software timer mode each of the modules can generate
an interrupt upon a compare.
For applications that require accurate pulse widths and edges the
PCA modules can be used as High Speed Outputs (HSO). The PCA
toggles the appropriate CEXn pin when there is a match between
the PCA timer and the modules compare registers.
The pulse width modulator mode for the PCA allows the conversion
of digital information into analog signals. Each of the 5 modules can
be used in this mode. The frequency of the PWM depends on the
clock source for the PCA. The 8-bit PWM output is generated by
comparing the low byte of the PCA (CL) with the module’s CCAPnL
SFR. When CL < CCAPnL, the output is high. When CL > CCAPnL,
the output is low.
POWER OFF FLAG
The Power Off Flag (POF) is set by on-chip circuitry when the VCC
level on the 87L51FA/FB rises from 0 to 3.3V. The POF bit can be
set or cleared by software allowing a user to determine if the reset is
the result of a power-on or a warm start after powerdown. The VCC
level must remain above 2.0V for the POF to remain unaffected by
the VCC level.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
Reset
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-on reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-on, the voltage on
VCC and RST must come up at the same time for a proper start-up.
Idle Mode
In the idle mode, the CPU puts itself to sleep while all of the on-chip
peripherals stay active. The instruction to invoke the idle mode is the
last instruction executed in the normal operating mode before the
idle mode is activated. The CPU contents, the on-chip RAM, and all
of the special function registers remain intact during this mode. The
idle mode can be terminated either by any enabled interrupt (at
which time the process is picked up at the interrupt service routine
and continued), or by a hardware reset which starts the processor in
the same manner as a power-on reset.
Power-Down Mode
To save even more power, a Power Down mode can be invoked by
software. In this mode, the oscillator is stopped and the instruction
that invoked Power Down is the last instruction executed. The
on-chip RAM and Special Function Registers retain their values until
the Power Down mode is terminated.
On the 87L51FA/FB either a hardware reset or external interrupt can
use an exit from Power Down. Reset redefines all the SFRs but
does not change the on-chip RAM. An external interrupt allows both
the SFRs and the on-chip RAM to retain their values.
To properly terminate Power Down the reset or external interrupt
should not be executed before VCC is restored to its normal
operating level and must be held active long enough for the
oscillator to restart and stabilize (normally less than 10ms).
With an external interrupt, INT0 and INT1 must be enabled and
configured as level-sensitive. Holding the pin low restarts the
oscillator but bringing the pin back high completes the exit. Once the
interrupt is serviced, the next instruction to be executed after RETI
will be the one following the instruction that put the device into
Power Down.
Design Consideration
• When the idle mode is terminated by a hardware reset, the device
normally resumes program execution, from where it left off, up to
two machine cycles before the internal rest algorithm takes
control. On-chip hardware inhibits access to internal RAM in this
event, but access to the port pins is not inhibited. To eliminate the
possibility of an unexpected write when Idle is terminated by reset,
the instruction following the one that invokes Idle should not be
one that writes to a port pin or to external memory.
ONCE™ Mode
The ONCE (“On-Circuit Emulation”) Mode facilitates testing and
debugging of systems using the 87L51FA/FB without the
87L51FA/FB having to be removed from the circuit. The ONCE
Mode is invoked by:
1. Pull ALE low while the device is in reset and PSEN is high;
2. Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins go into a float
state, and the other port pins and ALE and PSEN are weakly pulled
high. The oscillator circuit remains active. While the 87L51FA/FB is
in this mode, an emulator or test CPU can be used to drive the
circuit. Normal operation is restored when a normal reset is applied.
1996 Aug 16
3-155
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