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MB3832APFV(1999) データシートの表示(PDF) - Fujitsu

部品番号
コンポーネント説明
メーカー
MB3832APFV
(Rev.:1999)
Fujitsu
Fujitsu Fujitsu
MB3832APFV Datasheet PDF : 23 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
MB3832A
(VCC = 16 V, Ta = +25°C)
Parameter
Symbol
Pin
no.
Condition
Min.
Value
Typ.
Unit
Max.
Input offset voltage
VIO
10, 9
V+INC, V–INC = 2.4 V to
12.6 V
–2
2 mV
I+INC
10
V+INC = 12.7 V,
V–INC = 12.6 V
Input bias current
I–INC
9
V+INC = 0.1 V,
V–INC = 0 V
1
2
µA
–2
–1
µA
VO1
12
V+INC = 12.7 V,
V–INC = 12.6 V
2.25
2.5
2.75 V
Output voltage
VO2
12
V+INC = 12.8 V,
V–INC = 12.6 V
VO3
12
V+INC = 0.1 V,
V–INC = 0 V
4.5
5.0
5.5 V
2.25
2.5
2.75 V
Current detector
VO4
amplifier block
(Current Amp.) Common mode
input voltage range
VCM
12
V+INC = 0.2 V,
V–INC = 0 V
10, 9
4.5
5.0
5.5 V
0
VCC
V
Common mode
rejection ratio
CMRR
12
V+INC, V–INC = 2.4 V to
12.6 V
60
90
— dB
Voltage gain
AV
12 V–INC = 12.6 V
22.5
25
27.5 V/V
Frequency
bandwidth
BW
12 AV = 0 dB
500*
— kHz
Output resistance
RO
12 f = 10 kHz
20*
Maximum output
voltage width
VOM+
12
VOM–
12
VCC – 2.0 VCC – 1.6 —
V
50
200 mV
Output source
current
IOM–
12 VCOUT = 2.5 V
–7
–2 mA
Output sink current IOM+
12 VCOUT = 2.5 V
60
170
µA
PWM
comparator
block
(PWM Comp.)
Threshold voltage
Input bias current
Latch mode input
current
Input latch voltage
VT0
VT100
IDTC
IDTC
VDTC
19 Duty cycle = 0 %
19 Duty cycle = 100 %
16 VDTC = 0.4 V
16 VDTC = 2.5 V
16 IDTC = 100 µA
1.2
–1.0
270
1.3
1.9
–0.2
900
0.15
V
2.0 V
µA
µA
0.3 V
ON duty cycle
Dtr
19 VDTC = VREF/1.56
43
48
53 %
* : Standard design value
(Continued)
7

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