PDU53-1200C3 データシートの表示（PDF） - Data Delay Devices

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PDU53-1200C3

3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU53)

Data Delay Devices 

PDU53

DELAY LINE AUTOMATED TESTING

TEST CONDITIONS

INPUT:

Ambient Temperature: 25oC ± 3oC

Supply Voltage (Vcc): -4.5V ± 0.1V

Input Pulse:

Standard 100K ECL

levels

Source Impedance: 50Ω Max.

Rise/Fall Time:

1.0 ns Max. (measured

between 20% and 80%)

Pulse Width:

Period:

PWIN = 10ns

PERIN = 100ns

OUTPUT:

Load:

Cload:

Threshold:

50Ω to -2V

5pf ± 10%

(VOH + VOL) / 2

(Rising & Falling)

NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.

PULSE

GENERATOR

OUT

TRIG

IN DEVICE UNDER OUT

TEST (DUT)

REF

IN

TRIG

OSCILLOSCOPE

ADDRESS SELECT

Test Setup

TRISE

PWIN

PERIN

TFALL

INPUT

80%

VIH

80%

SIGNAL

50%

20%

50%

20%

VIL

TRISE

TFALL

OUTPUT

SIGNAL

50%

VOH

50%

VOL

Timing Diagram For Testing

Doc #98003

DATA DELAY DEVICES, INC.

4

3/18/98

Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

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