TDA8007BHL/C4,118 データシートの表示（PDF） - NXP Semiconductors.
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TDA8007BHL/C4,118 Datasheet PDF : 51 Pages
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NXP Semiconductors
TDA8007BHL
Multiprotocol IC card interface
TDA8007BHL
Product data sheet
Table 3.
Symbol
C82
Pin description …continued
Pin
12
PRES2
13
C42
14
CGND2
15
CLK2
16
VCC2
17
RST2
18
GND
19
VUP
20
SAP
21
SBP
22
VDDA
23
SBM
24
AGND
25
SAM
26
VDD
D0 to D7
RD
WR
CS
ALE
27
28, 29, 30, 31, 32, 33,
34, 35
36
37
38
39
INT
40
INTAUX
41
AD3
42
AD2
43
AD1
44
Description
auxiliary I/O for ISO C8 contact (synchronous cards,
for instance) for card 2
card 2 presence contact input (active high)
auxiliary I/O for ISO C4 contact (synchronous cards,
for instance) for card 2
ground for card 2; must be connected to GND
clock output to card 2 (ISO C3 contact)
card 2 supply output voltage (ISO C1 contact)
card 2 reset output (ISO C2 contact)
ground
connection for the step-up converter capacitor;
connect a low ESR capacitor of 220 nF to AGND
contact 1 for the step-up converter; connect a low
ESR capacitor of 220 nF between pins SAP
and SAM
contact 3 for the step-up converter; connect a low
ESR capacitor of 220 nF between pins SBP
and SBM
positive analog supply voltage for the step-up
converter; may be higher than VDD; decouple with a
good quality capacitor to GND
contact 4 for the step-up converter; connect a low
ESR capacitor of 220 nF between pins SBP
and SBM
analog ground for the step-up converter
contact 2 for the step-up converter; connect a low
ESR capacitor of 220 nF between pins SAP
and SAM
positive supply voltage; decouple with a good quality
capacitor to GND
input/output of data 0-7;
TDA8007BHL/C3 in case of mulitplexed
configuration: address 0-7
read or write selection input; high for read, low for
write
enable pin; same behavior as CS\ (active low)
chip select input (active low)
TDA8007BHL/C4: Not connected;
TDA8007BHL/C3: address latch enable input in
case of multiplexed configuration, connect to VDD in
non-multiplexed configuration
NMOS interrupt output (active low)
auxiliary interrupt input
register selection address 3 input
register selection address 2 input
register selection address 1 input
All information provided in this document is subject to legal disclaimers.
Rev. 9.1 — 18 June 2012
© NXP B.V. 2012. All rights reserved.
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