78Q2120 データシートの表示（PDF） - TDK Corporation

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78Q2120

10/100BASE-TX Ethernet Transceiver

TDK Corporation 

78Q2120

10/100BASE-TX

Ethernet Transceiver

MII (continued)

PIN

MDC

64-PIN 80-PIN TYPE

18

22

I

MDIO

17

21

I/O

DESCRIPTION

MANAGEMENT DATA CLOCK: MDC is the clock used for

transferring data via the MDIO pin.

MANAGEMENT DATA INPUT/OUTPUT: MDIO is a bi-directional port

used to access management registers within the 78Q2120. This pin

requires an external pull-up resistor as specified in IEEE-802.3.

PHY ADDRESS

PHYAD[4:0] 12-16

14-18

I PHY ADDRESS: Allows 31 configurable PHY addresses. The

78Q2120 always responds to data transactions via the MII interface

when the PHYAD bits are all zero independent of the logic levels of

the PHYAD pins.

PMA (PHYSICAL MEDIA ATTACHMENT) INTERFACE

PCSBP

64

1

I PCS BYPASS: When high, the 100BASE-TX PCS is bypassed, as

well as the scrambler and descrambler functions. Scrambled 5-bit

code groups for transmission are applied to the TX_ER, TXD[3:0]

pins and received on the RX_ER, RXD[3:0] pins. The RX_DV and

TX_EN signals are not valid in this mode. PCS bypass mode is only

valid when 100BASE-TX is enabled. This mode can also be entered

with MR16.1.

CONTROL AND STATUS

RST

6

8

PWRDN

7

9

ISO

2

3

ISODEF

1

2

I

RESET: When pulled low the pin resets the chip. The reset pulse

must be long enough to guarantee stabilization of Vcc and startup

of the oscillator. There are 2 other ways to reset the chip:

i) through the internal power-on-reset (activated when the chip

is being powered up)

ii) through the MII register bit (MR 0.15)

I POWER-DOWN: The 78Q2120 may be placed in a low power

consumption state by setting this signal to logic high. While in power-

down state, the 78Q2120 still responds to management transactions.

The same power-down state can also be achieved through the

PWRDN bit in the MII register (MR0.11).

I ISOLATE: When set to logic one, the 78Q2120 will present a high

impedance on its MII output pins. This allows for multiple chips to be

attached to the same MII interface. When the 78Q2120 is isolated, it

still responds to management transactions. The same high

impedance state can also be achieved through the ISO bit in the MII

register (MR0.10).

I ISOLATE DEFAULT: This pin determines the power-up/reset default

of the ISO bit (MR0.10). If it is connected to VDD (GND), ISO bit will

have a default value of 1 (0). When this signal is tied to VDD, it

allows multiple chips to be connected to the same MII interface.

7

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