ZXLB1600 データシートの表示（PDF） - Diodes Incorporated.

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ZXLB1600

LCD AND OLED BIAS BOOST CONVERTER - STN, CSTN SCREENS

Diodes Incorporated. 

OBSOLETE

Closest Alternative Part AP5727WUG-7

ZXLB1600

ELECTRICAL CHARACTERISTICS (Cont.)

Test conditions unless otherwise stated: VIN = 3.0V, TAMB = 25°C

Symbol Parameter

Conditions

Output voltage control by dc voltage applied to ‘ADJ’ pin

VADJ (nom)

VADJ

Internal reference voltage

Temperature coefficient of VADJ

External overdrive voltage range

on ‘ADJ’ pin for output voltage

control

‘ADJ’ pin floating, ‘EN’= VIN

IADJ

Input current into VADJ pin

0.5<VADJ < VADJ (NOM)

VSENSE

Default Output voltage

‘ADJ’ pin floating, ‘EN’= VIN

Output voltage control by PWM signal applied to ‘EN’ input

∆T/T

PWM duty cycle range at ‘EN’

input

10kHz(5) < f < 100kHz, VENH =VIN

fLPF

Internal low pass filter cut-off

frequency

ALPF

Filter attenuation

f=30kHz

Internal voltage setting resistors for output voltage

R1

Ref. Block diagram

R2

Enable input

VENL

Low level Input voltage

VENH

High level Input voltage

IENL

Low level input current

IENH

TEN(hold)

High level input current

Enable active hold time(6)

Low-battery detection circuit

Device in shutdown

Device active

VEN =0V

VEN =VIN

VEN switched from high to low

VLBT

Detection threshold

VIN falling

Temperature coefficient of VBLT

VBLHYS

Hysteresis

VIN rising

Ref (LBD) Internal reference voltage

VLBT (max) Maximum voltage on LBT pin

IBLOL

Low level output current

Output ‘on’

VBLOL

Low level output voltage

IBLOL = 0.5mA

IBLOH

High level output current

Output ‘off’ , VBLOH = 29V

VBLOH

High level output voltage

Output ‘off’

Internal voltage setting resistors for low-battery detection circuit

R3

Ref. block diagram

R4

Min Typ Max Units

1.23

V

40

ppm/ЊC

0.5

VADJ V

(NOM)

-10 ␮A

27

29 V

40

100 %

4

kHz

52.5

dB

317

k⍀

6.93

M⍀

0.4 V

1.4

Vin V

-100 nA

100 nA

120

␮s

1.94

2.02 V

20

ppm/ЊC

20

mV

1.21

V

Vin-0.5 V

1 mA

0.4 V

2 ␮A

29 V

1.56

M⍀

2.44

M⍀

Note:

5) This is the minimum PWM frequency to maintain a continuous output. Lower frequencies can be used, but will result in gated operation of

the device i.e. device enters shutdown when EN is low (see Note 6).

6) This is the time for which the device remains active after the EN pin has been driven low. This delay allows a continuous output to be

maintained during PWM mode operation at frequencies higher than 10kHz.

ISSUE 3 - SEPTEMBER 2003

3

SEMICONDUCTORS

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