MSC8122(2006) データシートの表示（PDF） - Freescale Semiconductor

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MSC8122
(Rev.:2006)

Quad Core 16-Bit Digital Signal Processor

Freescale Semiconductor 

Signals/Connections

1.4 Direct Slave Interface, System Bus, Ethernet, and

Interrupt Signals

The direct slave interface (DSI) is combined with the system bus because they share some common signal lines.

Individual assignment of a signal to a specific signal line is configured through internal registers. Table 1-5

describes the signals in this group.

Note:

Although there are fifteen interrupt request (IRQ) connections to the core processors, there are multiple

external lines that can connect to these internal signal lines. After reset, the default configuration enables

only IRQ[1–7], but includes two input lines each for IRQ[1–3] and IRQ7. The designer must select one line for

each required interrupt and reconfigure the other external signal line or lines for alternate functions.

Additional alternate IRQ lines and IRQ[8–15] are enabled through the GPIO signal lines.

Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals

Signal Name

HD0

Type

Input/ Output Host Data Bus 0

Bit 0 of the DSI data bus.

Description

SWTE

HD1

Input

Software Watchdog Timer Disable.

It is sampled on the rising edge of PORESET signal.

Input/ Output Host Data Bus 1

Bit 1 of the DSI data bus.

DSISYNC

HD2

Input

DSI Synchronous

Distinguishes between synchronous and asynchronous operation of the DSI. It is sampled on the rising

edge of PORESET signal.

Input/ Output Host Data Bus 2

Bit 2 of the DSI data bus.

DSI64

HD3

Input

DSI 64

Defines the width of the DSI and SYSTEM Data buses. It is sampled on the rising edge of PORESET

signal.

Input/ Output Host Data Bus 3

Bit 3 of the DSI data bus.

MODCK1

HD4

Input

Clock Mode 1

Defines the clock frequencies. It is sampled on the rising edge of PORESET signal.

Input/ Output Host Data Bus 4

Bit 4 of the DSI data bus.

MODCK2

HD5

Input

Clock Mode 2

Defines the clock frequencies. It is sampled on the rising edge of PORESET signal.

Input/ Output Host Data Bus 5

Bit 5 of the DSI data bus.

CNFGS

HD[6–31]

Input

Configuration Source

One signal out of two that indicates reset configuration mode. It is sampled on the rising edge of

PORESET signal.

Input/ Output Host Data Bus 6–31

Bits 6–31 of the DSI data bus.

MSC8122 Technical Data, Rev. 13

1-4

Freescale Semiconductor

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