MSC8122(2006) データシートの表示（PDF） - Freescale Semiconductor
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MSC8122 Datasheet PDF : 88 Pages
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Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals
Table 1-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)
Signal Name
HWBS[4–7]
Type
Input
Description
Host Write Byte Strobes (In Asynchronous dual mode)
One bit per byte is used as a strobe for host write accesses.
HDBS[4–7]
Input
Host Data Byte Strobe (in Asynchronous single mode)
One bit per byte is used as a strobe for host read or write accesses
HWBE[4–7]
Input
Host Write Byte Enable (In Synchronous dual mode)
One bit per byte is used to indicate a valid data byte for host write accesses.
HDBE[4–7]
Input
Host Data Byte Enable (in Synchronous single mode)
One bit per byte is used as a strobe enable for host read or write accesses
PWE[4–7]
Output
System Bus Write Enable
Outputs of the bus general-purpose chip-select machine (GPCM). These pins select byte lanes for write
operations.
PSDDQM[4–7]
Output
System Bus SDRAM DQM
From the SDRAM control machine. These pins select specific byte lanes of SDRAM devices.
PBS[4–7]
HRDS
Output
Input
System Bus UPM Byte Select
From the UPM in the memory controller, these signals select specific byte lanes during memory
operations. The timing of these pins is programmed in the UPM. The actual driven value depends on the
address and size of the transaction and the port size of the accessed device.
Host Read Data Strobe (In Asynchronous dual mode)
Used as a strobe for host read accesses.
HRW
Input
Host Read/Write Select (in Asynchronous/Synchronous single mode)
Host read/write select.
HRDE
HBRST
HDST[0–1]
Input
Input
Input
Host Read Data Enable (In Synchronous dual mode)
Indicates valid data for host read accesses.
Host Burst
The host asserts this pin to indicate that the current transaction is a burst transaction in synchronous
mode only.
Host Data Structure 0–1
Defines the data structure of the host access in DSI little-endian mode.
HA[9–10]
HCS
HBCS
HTA
HCLKIN
A[0–31]
TT0
Host Bus Address 9–10
Used by an external host to access the internal address space.
Input
Host Chip Select
DSI chip select. The DSI is accessed only if HCS is asserted and HCID[0–3] matches the Chip_ID.
Input
Host Broadcast Chip Select
DSI chip select for broadcast mode. Enables more than one DSI to share the same host chip-select pin for
broadcast write accesses.
Output
Host Transfer Acknowledge
Upon a read access, indicates to the host when the data on the data bus is valid. Upon a write access,
indicates to the host that the data on the data bus was written to the DSI write buffer.
Input
Host Clock Input
Host clock signal for DSI synchronous mode.
Input/ Output
Address Bus
When the MSC8122 is in external master bus mode, these pins function as the system address bus. The
MSC8122 drives the address of its internal bus masters and responds to addresses generated by external
bus masters. When the MSC8122 is in internal master bus mode, these pins are used as address lines
connected to memory devices and are controlled by the MSC8122 memory controller.
Input/ Output Bus Transfer Type 0
The bus master drives this pins during the address tenure to specify the type of the transaction.
HA7
Host Bus Address 7
Used by an external host to access the internal address space.
MSC8122 Technical Data, Rev. 13
Freescale Semiconductor
1-9
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