MSC8122(2006) データシートの表示（PDF） - Freescale Semiconductor

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MSC8122
(Rev.:2006)

Quad Core 16-Bit Digital Signal Processor

Freescale Semiconductor 

Features

Feature

Memory Controller

Multi-Channel DMA

Controller

Time-Division

Multiplexing (TDM)

Description

Flexible eight-bank memory controller:

• Three user-programmable machines (UPMs), general-purpose chip-select machine (GPCM), and a page-mode

SDRAM machine.

• Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash memory, and other user-definable

peripherals.

• Byte enables for either 64-bit or 32-bit bus width mode.

• Eight external memory banks (banks 0–7). Two additional memory banks (banks 9, 11) control IPBus

peripherals and internal memories. Each bank has the following features:

— 32-bit address decoding with programmable mask.

— Variable block sizes (32 KB to 4 GB).

— Selectable memory controller machine.

— Two types of data errors check/correction: normal odd/even parity and read-modify-write (RMW) odd/even

parity for single accesses.

— Write-protection capability.

— Control signal generation machine selection on a per-bank basis.

— Support for internal or external masters on the system bus.

— Data buffer controls activated on a per-bank basis.

— Atomic operation.

— RMW data parity check (on system bus only).

— Extensive external memory-controller/bus-slave support.

— Parity byte select pin, which enables a fast, glueless connection to RMW-parity devices (on the system bus

only).

— Data pipeline to reduce data set-up time for synchronous devices.

• 16 time-multiplexed unidirectional channels.

• Services up to four external peripherals.

• Supports DONE or DRACK protocol on two external peripherals.

• Each channel group services 16 internal requests generated by eight internal FIFOs. Each FIFO generates:

— A watermark request to indicate that the FIFO contains data for the DMA to empty and write to the destination.

— A hungry request to indicate that the FIFO can accept more data.

• Priority-based time-multiplexing between channels using 16 internal priority levels.

• Round-robin time-multiplexing between channels.

• A flexible channel configuration:

— All channels support all features.

— All channels connect to the system bus or local bus.

• Flyby transfers in which a single data access is transferred directly from the source to the destination without

using a DMA FIFO.

Up to four independent TDM modules, each with the following features:

• Optional operating configurations:

— Totally independent receive and transmit channels, each having one data line, one clock line, and one frame

sync line.

— Four data lines with one clock and one frame sync shared among the transmit and receive lines.

• Connects gluelessly to most T1/E1 framers as well as to common buses such as the ST-BUS.

• Hardware A-law/μ-law conversion.

• Up to 62.5 Mbps per TDM (62.5 MHz bit clock if one data line is used, 31.25 MHz if two data lines are used,

15.63 MHz if four data lines are used).

• Up to 256 channels.

• Up to 16 MB per channel buffer (granularity 8 bytes), where A/μ law buffer size is double (granularity 16 byte).

• Receive buffers share one global write offset pointer that is written to the same offset relative to their start

address.

• Transmit buffers share one global read offset pointer that is read from the same offset relative to their start

address.

• All channels share the same word size.

• Two programmable receive and two programmable transmit threshold levels with interrupt generation that can

be used, for example, to implement double buffering.

• Each channel can be programmed to be active or inactive.

• 2-, 4-, 8-, or 16-bit channels are stored in the internal memory as 2-, 4-, 8-, or 16-bit channels, respectively.

• The TDM Transmitter Sync Signal (TxTSYN) can be configured as either input or output.

• Frame Sync and Data signals can be programmed to be sampled either on the rising edge or on the falling edge

of the clock.

• Frame sync can be programmed as active low or active high.

• Selectable delay (0–3 bits) between the Frame Sync signal and the beginning of the frame.

• MSB or LSB first support.

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

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