IRS2541SPBF データシートの表示（PDF） - International Rectifier

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IRS2541SPBF

LED BUCK REGULATOR CONTROL IC

International Rectifier 

100

90

80

70

60

50

40

30

20

10

0

0

Enable Duty Cycle Relationship to Light Output

10

20

30

40

50

60

70

80

90

100

Percentage of Light Output

Fig.5 Light Output vs Enable Pin Duty Cycle

EN

HO

LO

Fig.6 IRS254(0,1) Dimming Signals

Open Circuit Protection Mode

By using the suggested

Vout

voltage

divider,

capacitor, and zener

R1

diode, the output

voltage can be clamped

at any desired value. In

open-circuit condition

IFB

3

EN

4

without output clamp,

R2

the positive output

terminal will float at the

high-side input voltage.

Switching will still occur

Fig.7 Open Circuit

Protection Scheme

between the HO and LO

outputs, whether due to the

output voltage clamp or the watchdog timer.

Transients and switching will be observed at the

positive output terminal as seen in Fig. 8. The

difference in signal shape, between the output

voltage and the IFB, is due to the capacitor used to

www.irf.com

IRS254(0,1)(S)PbF

form the voltage clamp. The repetition of the spikes

can be reduced by simply increasing the capacitor

size.

The two resistors form a voltage divider for the

output, which is then fed into the cathode of the

zener diode. The diode will only conduct, flooding

the enable pin, when its nominal voltage is

exceeded. The chip will enter a disabled state once

the divider network produces a voltage at least 2.5 V

greater than the zener rating. The capacitor serves

only to filter and slow the transients/switching at the

positive output terminal. The clamped output

voltage can be determined by the following analysis.

The choice of capacitor is at the designer’s

discretion.

Vout

=

(2.5V

+

DZ )(R1

R2

+ R2 )

DZ = Zener Diode Nominal Rated Voltage

Fig.8 Open Circuit Fault Signals, with Clamp

Under-voltage Lock-out Mode

The under-voltage lock-out mode (UVLO) is defined

as the state IRS254(0,1) is in when VCC is below the

turn-on threshold of the IC. During startup

conditions, if the IC supply remains below V , CCUV+ the

IRS254(0,1) will enter the UVLO mode. This state is

very similar to when the IC has been disabled via

control signals, except that LO is also held low.

When the supply is increased to , VCCUV+ the IC enters

the normal operation mode. If already in normal

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