Si3050 + Si3011/18/19
Table 3. DC Characteristics, VD = 3.0 to 3.6 V
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
High Level Input Voltage1
VIH
Low Level Input Voltage1
VIL
2.0
—
—
—
—
0.8
High Level Output Voltage
VOH
IO = –2 mA
2.4
—
—
Low Level Output Voltage
VOL
IO = 2 mA
—
—
0.35
AOUT High Level Voltage
VAH
IO = 10 mA
2.4
—
—
AOUT Low Level Voltage
VAL
IO = 10 mA
—
—
0.35
Input Leakage Current
Power Supply Current, Digital2
Total Supply Current, Sleep Mode2
Total Supply Current, Deep Sleep2,3
IL
–10
—
10
ID
VD pin
—
8.5
10
ID
PDN = 1, PDL = 0
—
5.0
6.0
ID
PDN = 1, PDL = 1
—
1.3
1.5
Notes:
1. VIH/VIL do not apply to C1A/C2A.
2. All inputs at 0.4 or VD – 0.4 (CMOS levels). All inputs are held static except clock and all outputs unloaded
(Static IOUT = 0 mA).
3. RGDT is not functional in this state.
Unit
V
V
V
V
V
V
µA
mA
mA
mA
Rev. 1.5
7