MAX6873 データシートの表示（PDF） - Maxim Integrated

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MAX6873

EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors

Maxim Integrated 

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

Detailed Description

The MAX6872/MAX6873 EEPROM-configurable, multi-

voltage supply sequencers/supervisors monitor several

voltage-detector inputs and four general-purpose logic

inputs, and feature programmable outputs for highly

configurable, power-supply sequencing applications.

The MAX6872 features six voltage-detector inputs and

eight programmable outputs, while the MAX6873 fea-

tures four voltage-detector inputs and five programma-

ble outputs. Manual reset and margin disable inputs

simplify board-level testing during the manufacturing

process. The MAX6872/MAX6873 feature an accurate

internal 1.25V reference.

All voltage detectors provide two configurable thresh-

olds for undervoltage/overvoltage or dual undervoltage

detection. One high-voltage input (IN1) provides detec-

tor threshold voltages from +1.25V to +7.625V in 25mV

increments or +2.5V to +13.2V in 50mV increments.

A bipolar input (IN2) provides detector threshold volt-

ages from ±1.25V to ±7.625V in 25mV increments, or

±2.5V to ±15.25V in 50mV increments. Positive inputs

(IN3–IN6) provide detector threshold voltages from

+0.5V to +3.05V in 10mV increments, or +1.0V to +5.5V

in 20mV increments.

The host controller communicates with the MAX6872/

MAX6873s’ internal 4kb user EEPROM, configuration

EEPROM, configuration registers, and fault registers

through an SMBus/I2C-compatible serial interface (see

Figure 1).

Programmable output options include active-high,

active-low, open-drain, weak pullup, push-pull, and

charge pump. Select the charge-pump output feature

to drive n-channel FETs for power-supply sequencing

(see the Applications Information section). The outputs

swing between 0 and (VABP + 5V) when configured for

charge-pump operation.

IN_

COMPARATORS

LOGIC NETWORK

FOR PO_

GPI_, MR,

MARGIN

OUTPUT

STAGES

PO_

WATCHDOG

TIMERS

GPI_

SDA,

SERIAL

SCL

INTERFACE

ANALOG

BLOCK

DIGITAL

BLOCK

REGISTER BANK

CONTROLLER

EEPROM

(USER AND

CONFIG)

Figure 1. Top-Level Block Diagram

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