MAX6874 データシートの表示（PDF） - Maxim Integrated

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MAX6874

EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors

Maxim Integrated 

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

Detailed Description

The MAX6874/MAX6875 EEPROM-configurable, multi-

voltage supply sequencers/supervisors monitor several

voltage detector inputs and general-purpose logic

inputs, and feature programmable outputs for highly

configurable power-supply sequencing applications.

The MAX6874 features six voltage detector inputs, four

general-purpose logic inputs, and eight programmable

outputs, while the MAX6875 features four voltage

detector inputs, three general-purpose logic inputs,

and five programmable outputs. Manual reset and mar-

gin disable inputs simplify board-level testing during

the manufacturing process. The MAX6874/MAX6875

feature an accurate internal 1.25V reference.

All voltage detectors provide configurable thresholds for

undervoltage detection. One high-voltage input (IN1)

provides detector threshold voltages from +1.25V to

+7.625V in 25mV increments or +2.5V to +13.2V in 50mV

increments. A positive input (IN2) provides detector

threshold voltages from +1.25V to +3.05V in 25mV incre-

ments or +2.5V to +5.5V in 50mV increments. Positive

inputs (IN3–IN6) provide detector threshold voltages

from +0.5V to +3.05V in 10mV increments or +1.0V to

+5.5V in 20mV increments.

The host controller communicates with the MAX6874/

MAX6875’s internal 4kb user EEPROM, configuration

EEPROM, and configuration registers through an

SMBus/I2C-compatible serial interface (see Figure 1).

Program the open-drain outputs as active-high or active-

low. Program each output to assert on any voltage detec-

tor input, general-purpose logic input, watchdog timer,

manual reset, or other output stages. Programmable tim-

ing delay blocks configure each output to wait between

25µs and 1600ms before de-asserting.

The MAX6874/MAX6875 feature a watchdog timer,

adding flexibility. Program the watchdog timer to assert

one or more programmable outputs. Program the watch-

dog timer to clear on a combination of one GPI_ input

and one programmable output, one of the GPI_ inputs

only, or one of the programmable outputs only. The initial

and normal watchdog timeout periods are independently

programmable from 6.25ms to 102.4s.

A virtual diode-ORing scheme selects the input that pow-

ers the MAX6874/MAX6875. The MAX6874/MAX6875

derive power from IN1 if VIN1 > +6.5V or from the highest

voltage on IN3–IN5 if VIN1 < +2.7V. The power source

cannot be determined if +4V < VIN1 < +6.5V and one

of VIN3 through VIN5 > +2.7V. The programmable out-

puts maintain the correct programmed logic state for

VABP > VUVLO. One of IN3 through IN5 must be

greater than +2.7V or IN1 must be greater than +4V for

device operation.

IN_

COMPARATORS

LOGIC NETWORK

FOR PO_

GPI_, MR,

MARGIN

OUTPUT

STAGES

PO_

WATCHDOG

TIMER

GPI_

SDA,

SERIAL

SCL

INTERFACE

ANALOG

BLOCK

REGISTER BANK

CONTROLLER

EEPROM

(USER AND

CONFIG)

DIGITAL

BLOCK

Figure 1. Top-Level Block Diagram

10 ______________________________________________________________________________________

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