MAX6875 データシートの表示（PDF） - Maxim Integrated

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MAX6875

EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors

Maxim Integrated 

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

A master device communicates to the MAX6874/

MAX6875 by transmitting the proper address followed by

command and/or data words. Each transmit sequence is

framed by a START (S) or REPEATED START (SR) condi-

tion and a STOP (P) condition. Each word transmitted

over the bus is 8 bits long and is always followed by an

acknowledge pulse.

SCL is a logic input, while SDA is a logic input/open-

drain output. SCL and SDA both require external pullup

resistors to generate the logic-high voltage. Use 4.7kΩ

for most applications.

Bit Transfer

Each clock pulse transfers one data bit. The data on

SDA must remain stable while SCL is high (Figure 3),

otherwise the MAX6874/MAX6875 register a START or

STOP condition (Figure 4) from the master. SDA and

SCL idle high when the bus is not busy.

Start and Stop Conditions

Both SCL and SDA idle high when the bus is not busy. A

master device signals the beginning of a transmission

with a START (S) condition (Figure 4) by transitioning

SDA from high to low while SCL is high. The master

device issues a STOP (P) condition (Figure 4) by transi-

tioning SDA from low to high while SCL is high. A STOP

condition frees the bus for another transmission. The bus

remains active if a REPEATED START condition is gener-

ated, such as in the block read protocol (see Figure 7).

Early STOP Conditions

The MAX6874/MAX6875 recognize a STOP condition at

any point during transmission except if a STOP condition

occurs in the same high pulse as a START condition. This

condition is not a legal I2C format. At least one clock

pulse must separate any START and STOP condition.

SDA

tSU:DAT

tLOW

SCL

tHD:STA

START

CONDITION

tHIGH

tR

tF

Figure 2. Serial-Interface Timing Details

tHD:DAT

SDA

tSU:STA

tHD:STA

REPEATED START

CONDITION

SDA

tBUF

tSU:STO

STOP

CONDITION

START

CONDITION

SCL

SCL S

P

DATA LINE STABLE, CHANGE OF

DATA VALID DATA ALLOWED

Figure 3. Bit Transfer

START

CONDITION

Figure 4. Start and Stop Conditions

STOP

CONDITION

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