MAX6875 データシートの表示（PDF） - Maxim Integrated
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MAX6875 Datasheet PDF : 40 Pages
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EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
Repeated START Conditions
A REPEATED START (SR) condition may indicate a
change of data direction on the bus. Such a change
occurs when a command word is required to initiate a
read operation (see Figure 7). SR may also be used
when the bus master is writing to several I2C devices
and does not want to relinquish control of the bus. The
MAX6874/MAX6875 serial interface supports continu-
ous write operations with or without an SR condition
separating them. Continuous read operations require
SR conditions because of the change in direction of
data flow.
Acknowledge
The acknowledge bit (ACK) is the 9th bit attached to any
8-bit data word. The receiving device always generates
an ACK. The MAX6874/MAX6875 generate an ACK
when receiving an address or data by pulling SDA low
during the 9th clock period (Figure 5). When transmitting
data, such as when the master device reads data back
from the MAX6874/MAX6875, the MAX6874/MAX6875
wait for the master device to generate an ACK.
Monitoring ACK allows for detection of unsuccessful data
transfers. An unsuccessful data transfer occurs if the
receiving device is busy or if a system fault has
occurred. In the event of an unsuccessful data transfer,
the bus master should reattempt communication at a
later time. The MAX6874/MAX6875 generate a NACK
after the slave address during a software reboot, while
writing to the EEPROM, or when receiving an illegal
memory address.
Slave Address
The MAX6874 slave address conforms to the following
table:
SA7
(MSB)
SA6
SA5
SA4
SA3
SA2
SA1
SA0
(LSB)
1
0
1
0
A1 A0
X
R/W
X = Don’t care.
The MAX6875 slave address conforms to the following
table:
SA7
(MSB)
SA6
SA5
SA4
SA3
SA2
SA1
SA0
(LSB)
1
0
1
0
0
A0
X
R/W
X = Don’t care.
SA7 through SA4 represent the standard interface
address (1010) for devices with EEPROM. SA3 and
SA2 correspond to the A1 and A0 address inputs of the
MAX6874/MAX6875 (hardwired as logic low or logic
high). A1 is internally set to 0 for the MAX6875. SA0 is a
read/write flag bit (0 = write, 1 = read).
The A0 and A1 address inputs allow up to four
MAX6874s or two MAX6875s to connect to one bus.
Connect A0 and A1 to GND or to the serial interface
power supply (see Figure 6).
START
CONDITION
1
SCL
CLOCK PULSE FOR ACKNOWLEDGE
2
8
9
SDA BY
TRANSMITTER
S
SDA BY
RECEIVER
Figure 5. Acknowledge
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