MAX6875 データシートの表示（PDF） - Maxim Integrated

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MAX6875

EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors

Maxim Integrated 

EEPROM-Programmable, Hex/Quad,

Power-Supply Sequencers/Supervisors

Pin Description

PIN

MAX6874 MAX6875

1

3

2

5

3

6

4

4

5

7

6

—

7

—

8

—

9, 10, 23,

24

1, 8, 9,10,

16, 17,

23–26, 32

NAME

PO2

PO3

PO4

GND

PO5

PO6

PO7

PO8

N.C.

FUNCTION

Programmable Output 2. Configurable active-high or active-low open-drain output. PO2 pulls

low with a 10µA internal current sink for +1V < VABP < VUVLO. PO2 assumes its programmed

conditional output state when ABP exceeds UVLO.

Programmable Output 3. Configurable active-high or active-low open-drain output. PO3 pulls

low with a 10µA internal current sink for +1V < VABP < VUVLO. PO3 assumes its programmed

conditional output state when ABP exceeds UVLO.

Programmable Output 4. Configurable active-high or active-low open-drain output. PO4 pulls

low with a 10µA internal current sink for +1V < VABP < VUVLO. PO4 assumes its programmed

conditional output state when ABP exceeds UVLO.

Ground

Programmable Output 5. Configurable active-high or active-low open-drain output. PO5 pulls

low with a 10µA internal current sink for +1V < VABP < VUVLO. PO5 assumes its programmed

conditional output state when ABP exceeds UVLO.

Programmable Output 6. Configurable active-high or active-low open-drain output. PO6 pulls

low with a 10µA internal current sink for +1V < VABP < VUVLO. PO6 assumes its programmed

conditional output state when ABP exceeds UVLO.

Programmable Output 7. Configurable active-high or active-low open-drain output. PO7 pulls

low with a 10µA internal current sink for +1V < VABP < VUVLO. PO7 assumes its programmed

conditional output state when ABP exceeds UVLO.

Programmable Output 8. Configurable active-high or active-low open-drain output. PO8 pulls

low with a 10µA internal current sink for +1V < VABP < VUVLO. PO8 assumes its programmed

conditional output state when ABP exceeds UVLO.

No Connection. Not internally connected.

Margin Input. Drive MARGIN low to hold PO_ in their existing states. Leave MARGIN

11

11

MARGIN unconnected or connect to DBP if unused. MARGIN overrides MR if both assert at the same

time. MARGIN is internally pulled up to DBP through a 10µA current source.

Manual Reset Input. MR to either assert PO_ into a programmed state or to have no effect on

12

12

MR PO_ when driving MR low (see Table 6). Leave MR unconnected or connect to DBP if unused.

MR is internally pulled up to DBP through a 10µA current source.

13

13

SDA Serial Data Input/Output (Open-Drain). SDA requires an external pullup resistor.

14

14

SCL Serial Clock Input. SCL requires an external pullup resistor.

15

15

A0

Address Input 0. Address inputs allow up to four MAX6874 or two MAX6875 connections on

one common bus. Connect A0 to GND or to the serial interface power supply.

16

—

A1

Address Input 1 (MAX6874 only). Address inputs allow up to four MAX6874 connections on

one common bus. Connect A1 to GND or to the serial interface power supply.

8 _______________________________________________________________________________________

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