MAX6885 データシートの表示（PDF） - Maxim Integrated
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MAX6885 Datasheet PDF : 34 Pages
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EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
TIMING CHARACTERISTICS
(VIN1–VIN4 or VCC = 2.7V to 5.8V, AUXIN = WDI = GND, MARGIN = MR = DBP, TA = -40°C to +85°C, unless otherwise noted. Typical
values are at TIN1 = +25°C.) (Notes 1, 2, 3)
PARAMETER
SYMBOL
TIMING CHARACTERISTICS (Figure 6)
Serial Clock Frequency
Clock Low Period
fSCL
tLOW
Clock High Period
Bus Free Time
START Setup Time
tHIGH
tBUF
tSU:STA
START Hold Time
STOP Setup Time
tHD:STA
tSU:STO
Data In Setup Time
Data In Hold Time
tSU:DAT
tHD:DAT
Receive SCL/SDA Minimum Rise
Time
tR
(Note 7)
CONDITIONS
MIN TYP MAX UNITS
400
kHz
1.3
µs
0.6
µs
1.3
µs
0.6
µs
0.6
µs
0.6
µs
100
ns
30
900
ns
20 +
0.1 x CBUS
ns
Receive SCL/SDA Maximum Rise
Time
tR
(Note 7)
300
ns
Receive SCL/SDA Minimum Fall
Time
tF
(Note 7)
20 +
0.1 x CBUS
ns
Receive SCL/SDA Maximum Fall
Time
tF
(Note 7)
300
ns
Transmit SDA Fall Time
Pulse Width of Spike Suppressed
EEPROM Byte Write Cycle Time
tF
CBUS = 400pF (Note 5)
tSP
(Note 8)
tWR
(Note 9)
20 +
0.1 x CBUS
300
ns
50
ns
11
ms
Note 1: 100% production tested at TA = +25°C and TA = +85°C. Specifications at TA = -40°C are guaranteed by design.
Note 2: Device may be supplied from IN1–IN4 or VCC.
Note 3: The internal supply voltage, measured at VCC, equals the maximum of IN1–IN4.
Note 4: VIN_ > 0.3 x ADC range.
Note 5: Does not include the inaccuracy of the 1.25V input reference voltage (MAX6884 only).
Note 6: DNL is implicitly guaranteed by design in a Σ∆ converter.
Note 7: CBUS = total capacitance of one bus line in picofarads. Rise and fall times are measured between 0.1 x VBUS and 0.9 x
VBUS.
Note 8: Input filters on SDA, SCL, and A0 suppress noise spikes <50ns.
Note 9: An additional cycle is required when writing to configuration memory for the first time.
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