MAX6887 データシートの表示（PDF） - Maxim Integrated
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MAX6887 Datasheet PDF : 13 Pages
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Hex/Quad, Power-Supply Supervisory Circuits
Table 2. MAX6888 Threshold Options
PART
MAX6888AETE
MAX6888BETE
MAX6888CETE
MAX6888DETE
MAX6888EETE
MAX6888FETE
MAX6888GETE
MAX6888HETE
MAX6888QETE
MAX6888IETE
MAX6888JETE
MAX6888KETE
MAX6888LETE
MAX6888METE
MAX6888NETE
MAX6888OETE
MAX6888PETE
MAX6888RETE
IN1
4.620
4.620
4.620
3.060
3.060
3.060
3.060
3.060
0.557
4.380
4.380
4.380
2.880
2.880
2.880
2.880
2.880
0.527
UV THRESHOLDS (V)
IN2
IN3
3.060
2.310
3.060
2.310
3.060
1.670
2.310
1.670
2.310
1.670
2.310
1.390
2.310
0.557
1.670
0.557
0.557
0.557
2.880
2.190
2.880
2.190
2.880
1.580
2.190
1.580
2.190
1.580
2.190
1.310
2.190
0.527
1.580
0.527
0.527
0.527
IN4
1.670
0.557
0.557
1.390
0.557
0.557
0.557
0.557
0.557
1.580
0.527
0.527
1.310
0.527
0.527
0.527
0.527
0.527
IN1
5.360
5.360
5.360
3.540
3.540
3.540
3.540
3.540
0.643
5.620
5.620
5.620
3.700
3.700
3.700
3.700
3.700
0.673
OV THRESHOLDS (V)
IN2
IN3
3.540
2.680
3.540
2.680
3.540
1.930
2.680
1.930
2.680
1.930
2.680
1.610
2.680
0.643
1.930
0.643
0.643
0.643
3.700
2.810
3.700
2.810
3.700
2.020
2.810
2.020
2.810
2.020
2.810
1.680
2.810
0.673
2.020
0.673
0.673
0.673
IN4
1.930
0.643
0.643
1.610
0.643
0.643
0.643
0.643
0.643
2.020
0.673
0.673
1.680
0.673
0.673
0.673
0.673
0.673
existing state while system-level testing occurs. Leave
MARGIN unconnected or connect to BP if unused. An
internal 10µA current source pulls MARGIN to BP.
MARGIN overrides MR if both are asserted at the
same time. The state of RESET, OV, and WDO does not
change while MARGIN = GND.
RESET, OV, and WDO Outputs
The MAX6887/MAX6888 feature three active-low open-
drain outputs: RESET, OV, and WDO. After power-up or
overvoltage/undervoltage conditions, RESET and OV
remain in their active states until their timeout periods
expire and no undervoltage/overvoltage conditions are
present (see Figure 2).
OV asserts when any monitored input is above its over-
voltage threshold and remains asserted until all inputs
are below their thresholds and its respective 25µs time-
out period expires. Connect OV to MR to bring RESET
low during an overvoltage condition. OV requires a
pullup resistor (unless connected to MR).
RESET asserts when any monitored input is below its
undervoltage threshold or MR is asserted. RESET
remains asserted for 200ms after all assertion-causing
conditions have been cleared. Configure RESET to
assert when the watchdog timer expires by connecting
WDO to MR. RESET requires a pullup resistor.
WDO asserts when the watchdog timer expires. See
the Configuring the Watchdog Timer section for a com-
plete description. WDO requires a pullup resistor.
Configuring the Watchdog Timer
A watchdog timer monitors microprocessor (µP) soft-
ware execution for a stalled condition and resets the µP
if it stalls. Connect the watchdog timer output WDO to
the reset input or a nonmaskable interrupt of the µP.
The watchdog timer features independent initial and
normal watchdog timeout periods of 102.4s and 1.6s,
respectively.
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