AM29F100T-75EI データシートの表示（PDF） - Advanced Micro Devices

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AM29F100T-75EI

1 Megabit (131,072 x 8-Bit/65,536 x 16-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory

Advanced Micro Devices 

FINAL

Am29F100T/Am29F100B

1 Megabit (131,072 x 8-Bit/65,536 x 16-Bit) CMOS 5.0 Volt-only,

Sector Erase Flash Memory

Advanced

Micro

Devices

DISTINCTIVE CHARACTERISTICS

s 5.0 V ± 10% for read and write operations

— Minimizes system level power requirements

s Compatible with JEDEC-standards

— Pinout and software compatible with

single-power-supply flash

— Superior inadvertent write protection

s Package options

— 44-pin SO

— 48-pin TSOP

s Minimum 100,000 write/erase cycles

guaranteed

s High performance

— 70 ns maximum access time

s Sector erase architecture

— One 16 Kbyte, two 8 Kbytes, one 32 Kbyte,

and one 64 Kbytes

— Any combination of sectors can be erased. Also

supports full chip erase.

s Sector protection

— Hardware method that disables any combina-

tion of sectors from write or erase operations.

Implemented using standard PROM program-

ming equipment.

s Embedded Erase Algorithms

— Automatically pre-programs and erases the

chip or any sector

GENERAL DESCRIPTION

The Am29F100 is a 1 Mbit, 5.0 Volt-only Flash memory

organized as 128 Kbytes of 8 bits each or 64 words of 16

bits each. The 1 Mbit of data is divided into 5 sectors of

one 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and one 64

Kbytes, for flexible erase capability. The 8 bits of data

will appear on DQ0–DQ7 or 16 bits on DQ0–DQ15. The

Am29F100 is offered in 44-pin SO and 48-pin TSOP

packages. This device is designed to be programmed

in-system with the standard system 5.0 Volt VCC supply.

12.0 Volt VPP is not required for program or erase op-

erations. The device can also be reprogrammed in stan-

dard EPROM programmers.

The standard Am29F100 offers access times of 70 ns,

90 ns, 120 ns, and 150 ns, allowing operation of high-

speed microprocessors without wait states. To elimi-

nate bus contention the device has separate chip

enable (CE), write enable (WE) and output enable

(OE) controls.

1-32

s Embedded Program Algorithms

— Automatically programs and verifies data at

specified address

s Data Polling and Toggle Bit feature for detec-

tion of program or erase cycle completion

s Ready/Busy output (RY/BY)

— Hardware method for detection of program or

erase cycle completion

s Erase Suspend/Resume

— Supports reading data from a sector not being

erased

s Low power consumption

— 20 mA typical active read current for Byte Mode

— 28 mA typical active read current for Word

Mode

— 30 mA typical program/erase current

s Enhanced power management for standby

mode

— 25 µA typical standby current

s Boot Code Sector Architecture

— T = Top sector

— B = Bottom sector

s Hardware RESET pin

— Resets internal state machine to the read mode

The Am29F100 is entirely command set compatible with

the JEDEC single-power-supply Flash standard.

Commands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as input to an internal state-machine which

controls the erase and programming circuitry. Write cy-

cles also internally latch addresses and data needed for

the programming and erase operations. Reading data

out of the device is similar to reading from 12.0 Volt

Flash or EPROM devices.

The Am29F100 is programmed by executing the pro-

gram command sequence. This will invoke the Embed-

ded Program Algorithm which is an internal algorithm

that automatically times the program pulse widths and

verifies proper cell margin. Erase is accomplished by

executing the erase command sequence. This will in-

voke the Embedded Erase Algorithm which is an inter-

nal algorithm that automatically preprograms the array if

Publication# 18926 Rev. B Amendment /0

Issue Date: November 1995

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