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FDMC4435BZ(2008) データシートの表示(PDF) - Fairchild Semiconductor

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FDMC4435BZ
(Rev.:2008)
Fairchild
Fairchild Semiconductor Fairchild
FDMC4435BZ Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
Electrical Characteristics TJ = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min Typ Max Units
Off Characteristics
BVDSS
BVDSS
TJ
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ID = -250µA, VGS = 0V
ID = -250µA, referenced to 25°C
VDS = -24V,
VGS = 0V,
TJ = 125°C
VGS = ±25V, VDS = 0V
-30
V
22
mV/°C
-1
µA
-100
±10
µA
On Characteristics
VGS(th)
VGS(th)
TJ
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
rDS(on)
Static Drain to Source On Resistance
gFS
Forward Transconductance
VGS = VDS, ID = -250µA
-1.0
ID = -250µA, referenced to 25°C
VGS = -10V, ID = -8.5A
VGS = -4.5V, ID = -6.3A
VGS = -10V, ID = -8.5A,
VDD = -5V, ID = -8.5A
TJ = 125°C
-1.9
-5.3
14.6
23.1
20.7
24
-3.0
V
mV/°C
20.0
37.0 m
28.0
S
Dynamic Characteristics
Ciss
Coss
Crss
Rg
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
VDS = -15V, VGS = 0V,
f = 1MHz
f = 1MHz
1540 2045 pF
295 395
pF
260 385
pF
5.1
Switching Characteristics
td(on)
tr
td(off)
tf
Qg
Qg
Qgs
Qgd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
VDD = -15V, ID = -8.5A,
VGS = -10V, RGEN = 6
VGS = 0V to -10V
VGS = 0V to -4.5V
VDD = -15V,
ID = -8.5A
10
20
ns
6
12
ns
34
55
ns
20
36
ns
33
46
nC
17
24
nC
5
nC
9
nC
Drain-Source Diode Characteristics
VSD
Source to Drain Diode Forward Voltage VGS = 0V, IS = -8.5A
VGS = 0V, IS = -1.9A
(Note 2)
(Note 2)
0.92
1.5
V
0.75
1.2
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IF = -8.5A, di/dt = 100A/µs
22
ns
11
nC
NOTES:
1: RθJA is determined with the device mounted on a 1in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by
the user's board design.
.
a. 53°C/W when mounted on
a 1 in2 pad of 2 oz copper
b. 125°C/W when mounted on a
minimum pad of 2 oz copper
2: Pulse Test: Pulse Width < 300µs, Duty cycle < 2.0%.
3. Starting TJ = 25°C, L = 1mH, IAS = -7A, VDD = -27V, VGS = -10V.
4. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
FDMC4435BZ Rev.C
2
www.fairchildsemi.com

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