C0603C824K8PACTU データシートの表示（PDF） - Unspecified
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C0603C824K8PACTU Datasheet PDF : 22 Pages
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Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
X5R Dielectric, 4 – 50 VDC (Commercial Grade)
Post Environmental Limits
Dielectric
X5R
High Temperature Life, Biased Humidity, Moisture Resistance
Rated DC
Voltage
Capacitance Dissipation Factor Capacitance
Value
(Maximum %)
Shift
< 1.0 µF
7.5
> 25
≥ 1.0 µF
20.0
Insulation
Resistance
< 2.2 µF
7.5
25
≥ 2.2 µF
20.0
±20%
10% of Initial
Limit
< 0.56 µF
7.5
< 25
≥ 0.56 µF
20.0
Dissipation Factor Limit Table
Rated
DC Voltage
> 25
25
< 25
Capacitance
< 1.0 µF
≥ 1.0 µF
< 2.2 µF
≥ 2.2 µF
< 0.56 µF
≥ 0.56 µF
Dissipation Factor
(Maximum %)
5.0
10.0
5.0
10.0
5.0
10.0
Insulation Resistance Limit Table
EIA Case Size
0201
0402
0603
0805
1206
1210
1812
1,000 Megohm
Microfarads or 100 GΩ
N/A
< .012 µF
< .047 µF
< 0.15 µF
< 0.47 µF
< 0.39 µF
< 2.2 µF
500 Megohm
Microfarads or 10 GΩ
ALL
≥ .012 µF < 1.0 µF
≥ .047 µf < 1.0 µF
≥ 0.15 µF < 1.0 µF
≥ 0.47 µF < 1.0 µF
≥ 0.39 µF < 1.0 µF
≥ 2.2 µF
100 Megohm
Microfarads
N/A
≥ 1.0 µF
≥ 1.0 µF
≥ 1.0 µF
≥ 1.0 µF
≥ 1.0 µF
N/A
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 • 864-963-6300 • www.kemet.com
C1006_X5R_SMD • 3/21/2017 4
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