LF48410 データシートの表示（PDF） - LOGIC Devices

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LF48410

1024 x 24-bit Video Histogrammer

LOGIC Devices 

DEVICES INCORPORATED

LF48410

1024 x 24-bit Video Histogrammer

FIGURE 3. LOOK UP TABLE MODE

24

DIN23-0

10

PIN9-0

CLK

(TO ALL REGISTERS)

START

RAM ARRAY

DATA IN

DATA OUT

ADDRESS WR

ADDRESS

GENERATOR

"0"

COUNTER

CONTROL

24

DIO

I/F

DIO23-0

RD

NOTE: NUMBER IN REGISTER INDICATES

NUMBER OF PIPELINE DELAYS.

FIGURE 4. BIN ACCUMULATE MODE

24

DIN23-0

10

PIN9-0

RAM ARRAY

DATA IN

DATA OUT

ADDRESS WR

ADDRESS

"0"

GENERATOR

24

DIO

I/F

DIO23-0

RD

START

CLK

CONTROL

TO ALL REGISTERS

NOTE: NUMBER IN REGISTER INDICATES

NUMBER OF PIPELINE DELAYS.

into the memory array at the address

defined by the counter. The value

already in the memory array at that

address is output on DIO23-0 (if RD is

LOW). Every rising edge of CLK

causes the counter to increment its

output by one until the counter

reaches a value of 1023. At this point,

the counter will hold the value of

1023 and writing to the memory array

will be disabled. DIN23-0 is delayed

internally three clock cycles to match

the latency of the address generator.

In Asynchronous 16/24 Mode, data is

loaded into the memory array as

detailed in the asynchronous mode

sections. If the Cumulative Distribu-

tion Function is the desired transfor-

mation function, the memory array

will contain this data as soon as the

Histogram Accumulate function has

been completed.

Once the memory array contains the

desired data, the device needs to be

put in Look Up Table Read Mode by

setting START HIGH. In Look Up

Table Read Mode, pixel values are

input on PIN9-0 and are latched on

the rising edge of CLK. Data at the

address defined by PIN9-0 is read out

of the memory array and output on

DIO23-0 (if RD is LOW). If Look Up

Table Write Mode was used to load

the memory array, it is important to

wait until the third clock cycle after

START goes HIGH to input data on

PIN9-0 to insure that all data is

written into the memory array before

any reading is done.

BIN ACCUMULATE MODE

When the LF48410 is in this mode, the

chip is configured as shown in Figure

4. PIN9-0 provides address data for

the memory array and is latched on

the rising edge of CLK. Data at the

address defined by PIN9-0 is read out

of the memory array and added to

the data on DIN23-0. This new value

is written back to the memory array,

in the same location where the last

read occured, and is also output on

DIO23-0 (if RD is LOW). As long as

START is LOW, the device will be

enabled for Bin Accumulate Mode.

When START is HIGH, the device will

still read address values on PIN9-0, but

the addressed data will not be added

to anything. The unchanged data will

be output on DIO23-0 and is not

written back to the memory array

(writing is disabled). START and

DIN23-0 are delayed internally three

clock cycles to match the latency of

the address generator.

DELAY MEMORY MODE

When the LF48410 is in this mode, the

chip is configured as shown in Figure

5. This mode allows the device to

function as a row buffer. The internal

counter is used to generate address

data for the memory array. When

START goes LOW, the counter is

reset to zero. Delay length (row

length) is determined by reseting the

counter every N–4 clock cycles, where

N is the number of delays. For

Video Imaging Products

4

08/08/2000–LDS.48410-L

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