IRS2111STRPBF データシートの表示（PDF） - International Rectifier

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IRS2111STRPBF

HALF-BRIDGE DRIVER

International Rectifier 

IRS2111(S)PbF

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-

eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured

under board mounted and still air conditions. Additional information is shown in Figs. 7 through 10.

Symbol Definition

Min.

VB

VS

VHO

VCC

VLO

VIN

dVs/dt

PD

High side floating supply voltage

High side floating supply offset voltage

High side floating output voltage

Low side and logic fixed supply voltage

Low side output voltage

Logic input voltage

Allowable offset supply voltage transient (Fig. 2)

(8 Lead PDIP)

Package power dissipation @ TA ≤ +25°C

(8 lead SOIC)

-0.3

VB - 25

VS - 0.3

-0.3

-0.3

-0.3

—

—

—

(8 lead PDIP)

—

RthJA

Thermal resistance, junction to ambient

(8 lead SOIC)

—

TJ

Junction temperature

—

TS

Storage temperature

-55

TL

Lead temperature (soldering, 10 seconds)

—

Note 1: All supplies are fully tested at 25 V, and an internal 20 V clamp exists for each supply

Max.

625 (Note 1)

VB + 0.3

VB + 0.3

25 (Note 1)

VCC + 0.3

VCC + 0.3

50

1.0

0.625

125

200

150

150

300

Units

V

V/ns

W

°C/W

°C

Recommended Operating Conditions

The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the

recommended conditions. The VS offset rating is tested with all supplies biased at a 15 V differential.

Symbol

VB

VS

VHO

VCC

VLO

VIN

TA

Definition

High side floating supply absolute voltage

High side floating supply offset voltage

High side floating output voltage

Low side and logic fixed supply voltage

Low side output voltage

Logic input voltage

Ambient temperature

Min.

VS + 10

Note 2

VS

10

0

0

-40

Max.

VS + 20

600

VB

20

VCC

VCC

125

Units

V

°C

Note 2: Logic operational for VS of -5 V to +600 V. Logic state held for VS of -5 V to -VBS. (Please refer to the Design Tip

DT97-3 for more details).

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