AP28F010-150 データシートの表示（PDF） - Intel

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AP28F010-150

1024K (128K x 8) CMOS FLASH MEMORY

Intel 

A28F010

With Chip-Enable and Output-Enable at a logic low

level raising A9 to high voltage VID (see DC Charac-

teristics) activates the operation Data read from lo-

cations 0000H and 0001H represent the manufac-

turer’s code and the device code respectively

The manufacturer- and device-codes can also be

read via the command register for instances where

the 28F010 is erased and reprogrammed in the tar-

get system Following a write of 90H to the com-

mand register a read from address location 0000H

outputs the manufacturer code (89H) A read from

address 0001H outputs the device code (B4H)

used to store the command along with address and

data information needed to execute the command

The command register is written by bringing Write-

Enable to a logic-low level (VIL) while Chip-Enable is

low Addresses are latched on the falling edge of

Write-Enable while data is latched on the rising

edge of the Write-Enable pulse Standard microproc-

essor write timings are used

Refer to A C Write Characteristics and the Erase

Programming Waveforms for specific timing

parameters

Write

Device erasure and programming are accomplished

via the command register when high voltage is ap-

plied to the VPP pin The contents of the register

serve as input to the internal state-machine The

state-machine outputs dictate the function of the

device

The command register itself does not occupy an ad-

dressable memory location The register is a latch

COMMAND DEFINITIONS

When low voltage is applied to the VPP pin the con-

tents of the command register default to 00H en-

abling read-only operations

Placing high voltage on the VPP pin enables read

write operations Device operations are selected by

writing specific data patterns into the command reg-

ister Table 3 defines these 28F010 register

commands

Table 3 Command Definitions

Command

Bus

Cycles

First Bus Cycle

Second Bus Cycle

Req’d Operation(1) Address(2) Data(3) Operation(1) Address(2) Data(3)

Read Memory

1

Write

X

00H

Read Intelligent Identifier Codes(4) 2

Write

X

90H

Read

IA

ID

Set-up Erase Erase(5)

2

Write

X

20H

Write

X

20H

Erase Verify(5)

2

Write

EA

A0H

Read

X

EVD

Set-up Program Program(6)

2

Write

X

40H

Write

PA

PD

Program Verify(6)

2

Write

X

C0H

Read

X

PVD

Reset(7)

2

Write

X

FFH

Write

X

FFH

NOTES

1 Bus operations are defined in Table 2

2 IA e Identifier address 00H for manufacturer code 01H for device code

EA e Address of memory location to be read during erase verify

PA e Address of memory location to be programmed

Addresses are latched on the falling edge of the Write-Enable pulse

3 ID e Data read from location IA during device identification (Mfr e 89H Device e B4H)

EVD e Data read from location EA during erase verify

PD e Data to be programmed at location PA Data is latched on the rising edge of Write-Enable

PVD e Data read from location PA during program verify PA is latched on the Program command

4 Following the Read Intelligent ID command two read operations access manufacturer and device codes

5 Figure 5 illustrates the Quick-Erase Algorithm

6 Figure 4 illustrates the Quick-Pulse Programming Algorithm

7 The second bus cycle must be followed by the desired command register write

7

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