NTE6821 データシートの表示（PDF） - NTE Electronics
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NTE6821 Datasheet PDF : 5 Pages
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Bus Timing Characteristics (Cont’d): (VCC = 5V ±5%, VSS = 0, TA = 0° to +70°C unless otherwise
specified)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Setup Time, Address and R/W Valid to tAS
Enable Positive Transition
160 –
– ns
Address Hold Time
tAH
10 –
– ns
Data Delay Time, Read
tDDR
–
– 320 ns
Data Hold Time, Read
Data Setup Time, Write
data Hold Time, Write
tDHR
tDSW
tDHW
10 –
195 –
10 –
– ns
– ns
– ns
Peripheral Timing Characteristics: (VCC = 5V ±5%, VSS = 0, TA = 0° to +70°C unless otherwise
specified)
Parameter
Symbol Min Max Unit
Peripheral Data Setup Time
tPDSU 200 –
ns
Peripheral Data Hold Time
tPDH
0
– ns
Delay Time, Enable negative transition to CA2 negative transition
tCA2
– 1.0 µs
Delay Time, Enable negative transition to CA2 positive transition
tRS1
– 1.0 µs
Rise and fall Times for CA1 and CA2 input signals
tr, tf
– 1.0 µs
Delay Time from CA1 active transition to CA2 positive transition
tRS2
– 2.0 µs
Delay Time, Enable negative transition to Peripheral Data Valid
tPDW
– 1.0 µs
Delay Time, Enable negative transition to Peripheral CMOS Data Valid PA0 – PA7, CA2 tCMOS – 2.0 µs
Delay Time, Enable positive transition to CB2 negative transition
tCB2
– 1.0 µs
Delay Time, Peripheral Data Valid to CB2 negative transition
Delay Time, Enable positive transition to CB2 postivie transition
Peripheral Control Output Pulse Width, CA2/CB2
Rise and Fall Time for CB1 and CB2 input signals
Delay Time, CB1 active transition to CB2 positive transition
Interrupt Release Time, IRQA and IRQB
Interrupt Response Time
Interrupt Input Pulse Width
Reset Low Time (Note 2)
tDC
20
–
ns
tRS1
– 1.0 µs
PWCT 550 –
ns
tr, tf
– 1.0 µs
tRS2
– 2.0 µs
tIR
– 2.0 µs
tRS3
– 1.0 µs
PWI 500 – ns
tRL
1.0 –
µs
Note 2. The Reset line must be high a minimum of 1.0µs before addressing the PIA.
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