CY62128EV30LL-55ZXET(2012) データシートの表示（PDF） - Cypress Semiconductor

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CY62128EV30LL-55ZXET
(Rev.:2012)

1-Mbit (128 K × 8) Static RAM

Cypress Semiconductor 

CY62128EV30 MoBL® Automotive

Data Retention Characteristics

Over the Operating Range

Parameter

Description

VDR

ICCDR[10]

VCC for data retention

Data retention current

tCDR[11]

tR[12]

Chip deselect to data

retention time

Operation recovery time

Conditions

VCC = 1.5 V,

CE1 > VCC 0.2 V or

CE2 < 0.2 V,

VIN > VCC 0.2 V or

VIN < 0.2 V

Automotive-A

Automotive-E

Min Typ [9] Max Unit

1.5

–

–

V

–

–

3

A

–

–

30

A

0

–

–

ns

CY62128EV30LL-45

45

–

CY62128EV30LL-55

55

–

–

ns

–

Data Retention Waveform

Figure 5. Data Retention Waveform [13]

DATA RETENTION MODE

VCC

VCC(min)

VDR > 1.5V

tCDR

CE

VCC(min)

tR

Notes

9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.

10. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.

11. Tested initially and after any design or process changes that may affect these parameters.

12. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min)  100 s.

13. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.

Document #: 001-65528 Rev. *B

Page 7 of 18

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