CY62128EV30LL-55ZXET(2012) データシートの表示（PDF） - Cypress Semiconductor
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CY62128EV30LL-55ZXET Datasheet PDF : 18 Pages
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CY62128EV30 MoBL® Automotive
Switching Waveforms
Figure 6. Read Cycle 1 (Address Transition Controlled) [20, 21]
tRRCC
Address
DATA I/O
tAA
tOHA
Previous Data Valid
DATAOUTVALID
Figure 7. Read Cycle No. 2 (OE Controlled) [21, 22, 23]
Address
CE
OE
DATA I/O
VCC
Supply
Current
ADDRESS
CE
tRC
tACE
tDOE
tLZOE
tHZOE
tHZCE
High
High Impedance
DATAOUTVALID
Impedance
tLZCE
tPU
tPD
ICC
50%
50%
ISB
Figure 8. Write Cycle No. 1 (WE Controlled) [19, 22, 24, 25]
tWC
tSCE
tAW
tHA
tSA
tPWE
WE
OE
tSD
tHD
DATA I/O
NOTE 26
DATAINVALID
tHZOE
Notes
19. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
20. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
21. WE is HIGH for read cycle.
22. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
23. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH.
24. Data I/O is high impedance if OE = VIH.
25. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
26. During this period, the I/Os are in output state. Do not apply input signals.
Document #: 001-65528 Rev. *B
Page 9 of 18
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