73S1210F-44IM/F/P データシートの表示（PDF） - Teridian Semiconductor Corporation

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73S1210F-44IM/F/P

Self-Contained Smart Card Reader with PINpad and Power Management

Teridian Semiconductor Corporation 

DS_1210F_001

73S1210F Data Sheet

1.2 Hardware Overview

The 73S1210F single smart card controller integrates all primary functional blocks required to implement

a smart card reader. Included on chip are an 8051-compatible microprocessor (MPU) which executes up

to one instruction per clock cycle (80515), a fully integrated IS0 7816 compliant smart card interface,

expansion smart card interface, serial interface, I2C interface, 6 x 5 keypad interface, RAM, FLASH

memory, and a variety of I/O pins.

The power management circuitry provides a 3.3V voltage output (VDD, pin #68) that must be connected

to the power supply inputs of the digital core of the circuit, pins # 28 and 40 (these are not internally

connected). Should external circuitry require a 3.3V digital power supply, the VDD output is capable of

supplying additional current.

Figure 1 shows a functional block diagram of the 73S1210F.

1.3 80515 MPU Core

1.3.1 80515 Overview

The 73S1210F includes an 80515 MPU (8-bit, 8051-compatible) that performs most instructions in one

clock cycle. The 80515 architecture eliminates redundant bus states and implements parallel execution

of fetch and execution phases. Normally a machine cycle is aligned with a memory fetch, therefore, most

of the 1-byte instructions are performed in a single cycle. This leads to an 8x performance (average)

improvement (in terms of MIPS) over the Intel 8051 device running at the same clock frequency.

Actual processor clocking speed can be adjusted to the total processing demand of the application

(cryptographic calculations, key management, memory management, and I/O management) using the

XRAM special function register MPUCKCtl.

Typical smart card, serial, keyboard and I2C management functions are available for the MPU as part of

the Teridian standard library. A standard ANSI “C” 80515-application programming interface library is

available to help reduce design cycle. Refer to the 73S12xxF Software User’s Guide.

1.3.2 Memory Organization

The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces.

Memory organization in the 80515 is similar to that of the industry standard 8051. There are three

memory areas: Program memory (Flash), external data memory (XRAM), and internal data memory

(IRAM). Data bus address space is allocated to on-chip memory as shown Table 2

Table 2: MPU Data Memory Map

Address

(hex)

0000-7FFF

0000-07FF

FC00-FFFF

Memory

Technology

Flash Memory

Static RAM

External SFR

Memory Type

Typical Usage

Non-volatile

Volatile

Volatile

Program and non-volatile data

MPU data XRAM

Peripheral control

Memory Size

(bytes)

32KB

2KB

1KB

Note: The IRAM is part of the core and is addressed differently.

Program Memory: The 80515 can address up to 32KB of program memory space from 0x0000 to

0xFFFF. Program memory is read when the MPU fetches instructions or performs a MOVC operation.

After reset, the MPU starts program execution from location 0x0000. The lower part of the program

memory includes reset and interrupt vectors. The interrupt vectors are spaced at 8-byte intervals, starting

from 0x0003. Reset is located at 0x0000.

Flash Memory: The program memory consists of flash memory. The flash memory is intended to

primarily contain MPU program code. Flash erasure is initiated by writing a specific data pattern to

Rev. 1.4

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