73S1210F-IM68DK データシートの表示（PDF） - Teridian Semiconductor Corporation

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73S1210F-IM68DK

Self-Contained Smart Card Reader with PINpad and Power Management

Teridian Semiconductor Corporation 

73S1210F Data Sheet

DS_1210F_001

Figures

Figure 1: IC Functional Block Diagram ......................................................................................................... 7

Figure 2: Memory Map ................................................................................................................................ 15

Figure 3: Clock Generation and Control Circuits ........................................................................................ 22

Figure 4: Oscillator Circuit........................................................................................................................... 24

Figure 5: Detailed Power Management Logic Block Diagram .................................................................... 25

Figure 6: Power Down Control.................................................................................................................... 27

Figure 7: Detail of Power Down Interrupt Logic .......................................................................................... 28

Figure 8: Power Down Sequencing ............................................................................................................ 29

Figure 9: External Interrupt Configuration................................................................................................... 33

Figure 10: I2C Write Mode Operation.......................................................................................................... 55

Figure 11: I2C Read Operation ................................................................................................................... 56

Figure 12: Simplified Keypad Block Diagram ............................................................................................. 61

Figure 13: Keypad Interface Flow Chart ..................................................................................................... 63

Figure 14: Smart Card Interface Block Diagram......................................................................................... 69

Figure 15: External Smart Card Interface Block Diagram .......................................................................... 70

Figure 16: Asynchronous Activation Sequence Timing .............................................................................. 73

Figure 17: Deactivation Sequence.............................................................................................................. 73

Figure 18: Smart Card CLK and ETU Generation ...................................................................................... 74

Figure 19: Guard, Block, Wait and ATR Time Definitions .......................................................................... 75

Figure 20: Synchronous Activation ............................................................................................................. 77

Figure 21: Example of Sync Mode Operation: Generating/Reading ATR Signals ..................................... 77

Figure 22: Creation of Synchronous Clock Start/Stop Mode Start Bit in Sync Mode ................................. 78

Figure 23: Creation of Synchronous Clock Start/Stop Mode Stop Bit in Sync Mode ................................. 78

Figure 24: Operation of 9-bit Mode in Sync Mode ...................................................................................... 79

Figure 25: 73S1210F Typical Application Schematic ............................................................................... 104

Figure 26: 12 MHz Oscillator Circuit ......................................................................................................... 112

Figure 27: 32KHz Oscillator Circuit........................................................................................................... 112

Figure 28: Digital I/O Circuit ...................................................................................................................... 113

Figure 29: Digital Output Circuit................................................................................................................ 113

Figure 30: Digital I/O with Pull Up Circuit.................................................................................................. 114

Figure 31: Digital I/O with Pull Down Circuit ............................................................................................. 114

Figure 32: Digital Input Circuit................................................................................................................... 115

Figure 33: OFF_REQ Interface Circuit ..................................................................................................... 115

Figure 34: Keypad Row Circuit ................................................................................................................. 115

Figure 35: Keypad Column Circuit ............................................................................................................ 116

Figure 36: LED Circuit............................................................................................................................... 116

Figure 37: Test and Security Pin Circuit ................................................................................................... 117

Figure 38: Analog Input Circuit ................................................................................................................. 117

Figure 39: Smart Card Output Circuit ....................................................................................................... 117

Figure 40: Smart Card I/O Circuit ............................................................................................................. 118

Figure 41: PRES Input Circuit ................................................................................................................... 118

Figure 42: PRESB Input Circuit ................................................................................................................ 118

Figure 43: ON_OFF Input Circuit .............................................................................................................. 119

Figure 44: 73S1210F 68 QFN Pinout ....................................................................................................... 120

Figure 45: 73S1210F 44 QFN Pinout ....................................................................................................... 121

Figure 46: 73S1210F 68 QFN Mechanical Drawing ................................................................................. 122

Figure 47: 73S1210F 44 QFN Package Drawing ..................................................................................... 123

4

Rev. 1.4

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