K9F1G08U0D データシートの表示（PDF） - Samsung
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コンポーネント説明
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K9F1G08U0D Datasheet PDF : 39 Pages
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K9F1G08U0D
FLASH MEMORY
2.4 VALID BLOCK
Parameter
Symbol
Min
Typ.
Max
Unit
K9F1G08U0D
NVB
1,004
-
1,024
Blocks
Note :
1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks
is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or
program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to TBD program/erase cycles with 1bit/528Byte ECC.
2.5 AC TEST CONDITION
(K9F1G08U0D-XCB0 :TA=0 to 70°C, K9F1G08U0D-XIB0:TA=-40 to 85°C, K9F1G08U0D : Vcc=2.7V~3.6V unless otherwise noted)
Parameter
K9F1G08U0D
Input Pulse Levels
0V to Vcc
Input Rise and Fall Times
5ns
Input and Output Timing Levels
Vcc/2
Output Load
1 TTL GATE and CL=50pF
2.6 CAPACITANCE(TA=25°C, VCC=3.3V, f=1.0MHz)
Item
Symbol
Test Condition
Min
Max
Unit
Input/Output Capacitance
CI/O
VIL=0V
-
8
pF
Input Capacitance
CIN
VIN=0V
-
8
pF
Note : Capacitance is periodically sampled and not 100% tested.
2.7 MODE SELECTION
CLE
ALE
CE
WE
RE
H
L
L
H
L
H
L
H
H
L
L
H
L
H
L
H
L
L
L
H
L
L
L
H
X
X
X
X
H
X
X
X
X
X
X
X
X
X
X
X
X(1)
X
X
X
X
X
H
X
X
Note : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
WP
X
X
H
H
H
X
X
H
H
L
0V/VCC(2)
Mode
Command Input
Read Mode
Address Input(4clock)
Command Input
Write Mode
Address Input(4clock)
Data Input
Data Output
During Read(Busy)
During Program(Busy)
During Erase(Busy)
Write Protect
Stand-by
Samsung Confidential
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