K9F1G08U0D データシートの表示（PDF） - Samsung

部品番号

コンポーネント説明

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K9F1G08U0D

128M x 8 Bit NAND Flash Memory

Samsung 

K9F1G08U0D

FLASH MEMORY

2.0 Product Introduction

NAND Flash Memory has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system

upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written

through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and

Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require

one bus cycle. For example, Reset Command, Status Read Command, etc. require just one cycle bus. Some other commands, like

page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution.. Page Read

and Page Program need the same five address cycles following the required command input. In Block Erase operation, however,

only the three row address cycles are used. Device operations are selected by writing specific commands into the command regis-

ter. Table 1 defines the specific commands of the K9G1G08U0D.

Table 1. Command Sets

Function

1st Cycle

Read

00h

Read for Copy Back

00h

Read ID

90h

Reset

FFh

Page Program

80h

Copy-Back Program

85h

Block Erase

60h

Random Data Input(1)

85h

Random Data Output(1)

05h

Read Status

70h

Note : 1. Random Data Input/Output can be executed in a page.

2nd Cycle

30h

35h

-

-

10h

10h

D0h

-

E0h

-

Acceptable Command during Busy

O

O

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

Samsung Confidential

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