K9F1G08U0B-P データシートの表示（PDF） - Samsung

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K9F1G08U0B-P

128M x 8 Bit NAND Flash Memory

Samsung 

K9F1G08U0B

FLASH MEMORY

Product Introduction

The K9F1G08U0B is a 1,056Mbit(1,107,296,256 bit) memory organized as 65,536 rows(pages) by 2,112x8 columns. Spare 64x8 col-

umns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommodat-

ing data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up

of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of

two NAND structured strings. A NAND structure consists of 32 cells. Total 1,081,344 NAND cells reside in a block. The program and

read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of

1,024 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9F1G08U0B.

The K9F1G08U0B has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades

to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by

bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch

Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For

example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block

erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 132M byte physical space

requires 28 addresses, thereby requiring four cycles for addressing : 2 cycles of column address, 2 cycles of row address, in that

order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase oper-

ation, however, only the two row address cycles are used. Device operations are selected by writing specific commands into the com-

mand register. Table 1 defines the specific commands of the K9F1G08U0B.

In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another

page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and

data-input cycles are removed, system performance for solid-state disk application is significantly increased.

Table 1. Command Sets

Function

1st Cycle

Read

00h

Read for Copy Back

00h

Read ID

90h

Reset

FFh

Page Program

80h

Copy-Back Program

85h

Block Erase

60h

Random Data Input(1)

85h

Random Data Output(1)

05h

Read Status

70h

Read EDC Status(2)

7Bh

NOTE : 1. Random Data Input/Output can be executed in a page.

2. Read EDC Status is only available on Copy Back operation.

2nd Cycle

30h

35h

-

-

10h

10h

D0h

-

E0h

Acceptable Command during Busy

O

O

O

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

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